Dense arrays and charge storage devices

ABSTRACT

There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

This application is a divisional of U.S. application Ser. No.10/842,008, filed on May 10, 2004, which is a divisional of U.S.application Ser. No. 09/927,648 filed on Aug. 13, 2001, now U.S. Pat.No. 6,881,994, which are incorporated by reference in their entirety.Application Ser. No. 09/927,648 is a continuation-in-part of U.S.application Ser. No. 09/801,233, filed on Mar. 6, 2001, which is acontinuation-in-part of U.S. application Ser. No. 09/745,125, filed onDec. 21, 2000, both of which are incorporated by reference in theirentirety. Application Ser. No. 09/927,648 is also a continuation-in-partof U.S. application Ser. No. 09/639,579 filed on Aug. 14, 2000, which isincorporated by reference in its entirety. Application Ser. No.09/927,648 is also a continuation-in-part of U.S. application Ser. No.09/639,702 filed on Aug. 14, 2000, which is incorporated by reference inits entirety. Application Ser. No. 09/927,648 is also acontinuation-in-part of U.S. application Ser. No. 09/639,749 filed onAug. 17, 2000, which is incorporated by reference in its entirety.Application Ser. No. 09/927,648 also claims benefit of priority ofprovisional application 60/279,855, filed on Mar. 28, 2001, which isincorporated by reference in its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to semiconductor devices in general and toa three dimensional TFT array in particular.

2. Discussion of Related Art

As integrated circuits and computers have become powerful, newapplications have arisen that require the ability to store large amountsof data. Certain applications require a memory with the ability to writeand erase data and the ability to store data in a nonvolatile manner.There are many applications which can be enabled by bringing the priceper megabyte of semiconductor memory down well below a dollar (US) permegabyte so that it becomes price competitive with, for example: (1)chemical film for the storage of photographic images; (2) Compact Disks(CDs) for the storage of music and textual data for distribution; (3)Digital Versatile Disks (DVDs) for the storage of video and multi-mediamaterials for distribution; and (4) Video Tape and Digital Audio andVideo Tape for the storage of consumer audio and video recordings. Suchmemories should be archival and non-volatile in that they should be ableto withstand being removed from equipment and all sources of power for aperiod of up to about 10 years with no significant degradation of theinformation stored in them. Such a requirement approximates the typicallongevity for CDs, DVDs, magnetic tape and most forms of photographicfilm.

Presently, such memories are formed with electrically erasablenonvolatile memories such as flash memories and EEPROMs. Unfortunately,these devices are typically fabricated in a single crystalline siliconsubstrate and therefore are limited to two-dimensional arrays of storagedevices, thereby limiting the amount of data that can be stored to thenumber of devices that can be fabricated in a single plane of silicon.

It has also been known to fabricate nonvolatile memories that employedtrapped charge in a dielectric layer. Typically, electrons are trappedin a layer of silicon nitride by, for instance, tunneling a currentthrough the nitride layer. The silicon nitride is formed between a gateinsulated from the channel of a field-effect transistor. The trappedcharge shifts the threshold voltage of the transistor and thus, thethreshold voltage is sensed to determine whether or not charge istrapped in the nitride layer. See U.S. Pat. No. 5,768,192 for an exampleof such memories.

U.S. Pat. No. 5,768,192, issued to B. Eitan, and the technical articleentitled “NROM: A Novel Localized Trapping, 2-Bit Nonvolatile MemoryCell” by B. Eitan et al. in IEEE Electron Device Letters, vol. 21, No.11, November 2000, pp. 543-545 teach a nonvolatile semiconductor memorycell which uses asymmetrical charge trapping in the nitride chargestorage layer of the Oxide-Nitride-Oxide (ONO) stack to store two bitsin one cell. The cell is written by hot electron injection into thecharge storage layer above the drain junction. The cell is read in theopposite direction to which it was written, i.e., voltages are appliedto the source and gate, with the drain grounded. The memory cell isconstructed in a p-type silicon substrate. However, thissilicon-oxide-nitride-oxide-silicon (SONOS) ITC memory is arranged in anNOR Virtual Ground Array with a cell area of 2.5 F² per bit, where F isthe minimum feature size. This cell area is larger than desirable, andleads to a less than optimum cell density.

Prior art negative-resistance devices are also known. These devices werediscovered around 1972 and are described in Thin-MIS-Structure SiNegative-Resistance Diode, Applied Physics Letters, Volume 20, No. 8,beginning on page 269, 15 Apr. 1972. The device described in the articleis a junction diode, such as diode 5510 of FIG. 96 and a thin oxideregion disposed on the n-type region of the diode, such as the oxideregion 5511 of FIG. 96. The device provides a switching phenomenonexhibiting a negative-resistance region as shown in FIG. 97. Note as thepotential on the diode is increased in the diode's forward direction,little conduction occurs until the voltage first reaches the voltageshown as point 5512 at which point the device exhibits anegative-resistance. From there the device exhibits a somewhatdiode-like characteristic as shown by the segment 5513 in FIG. 97. Thisswitching characteristic is used to fabricate static memory cells(flip-flops) such as shown in U.S. Pat. Nos. 5,535,156 and 6,015,738.Additionally, the basic operation of this device is described in Sze's,The Physics of Semiconductor Devices, (2^(nd) edition, Chapter 9.5, pp.549-553), although this explanation may contain an error in itsdiscussion in polarity.

The device of FIG. 96 comprises a PN junction diode and a thin oxideregion. When the diode is forward biased, initially very little currentflows because the diode junction voltage is a fraction of the appliedvoltage, with the balance of the voltage drop across the n− region andoxide region. Holes injected into the n− region from the p region aresufficiently low in number that the tunneling current through the oxide(despite the unfavorable barrier to the hole flow) allows the n− regionto remain an n-type region. Similarly, any holes generated within thedepletion region are able to pass through the thin oxide while anygenerated electrons are swept across to the p region and out of theanode contact.

As the applied forward voltage increases, the n− region begins todeplete at the interface with the oxide just as in a normal MOSFET asthe threshold voltage is approached. At a high enough voltage, thisdepletion region extends all the way to the junction to producepunch-through, resulting in a significant injection of holes from the pregion into the n-layer. The holes cannot flow well through the oxideand consequently build up near the surface. This causes the n− region toinvert more strongly near the oxide interface, and increasing thevoltage drop across the oxide, recalling that V=Q/C. The electrontunneling current through the oxide rises by a super-exponential factor,increasing the forward bias across the diode and the current. At thesame time holes flood the n− region, raising its conductivity andreducing its voltage drop. Since the voltage across the diode isrelatively small (and changes little, even for large changes in current)a large reduction in the n-voltage drop reduces the voltage across theentire structure dramatically (assuming a suitable series resistance inthe circuit to avoid device rupture). Thus, the regenerative action ofthe foregoing description causes a rapid increase in current,accompanied by a rapid decrease in voltage. It is thisnegative-resistance region that has been exploited to make the SRAMcells described in the above referenced patents.

At higher current levels, the device behaves essentially as an ordinaryforward biased diode as most of the voltage is ultimately dropped acrossthe PN junction. Overall, the V-I characteristics of the structure areshown in FIG. 97 with the slope of the segment 5513 being determined inlarge part by the series resistance coupled to the structure of FIG. 96.

When reverse biased, the diode is in its blocking state and the onlycurrent that flows through the oxide is electron leakage current. Thereverse junction voltage is a fraction of the applied voltage becausesome is dropped across the oxide region. It should be noted thatelectrons carry current through the oxide region in both reverse biasand in a strong forward bias.

Another type of prior art memory device is disclosed in the technicalarticle entitled “A Novel Cell Structure for Giga-bit EPROMs and FlashMemories Using Polysilicon Thin Film Transistors” by S. Koyama in 1992Symposium on VLSI Technology Digest of Technical Papers, pp. 44-45. Asshown in FIG. 98, each memory cell is a “self-aligned” floating gatecell and contains a polycrystalline silicon thin film transistorelectrically erasable programmable read only memory (TFT EEPROM) over aninsulating layer. In this device, the bit lines extend in the directionparallel to the source-channel-drain direction (i.e., the bit linesextend parallel to the charge carrier flow direction). The word linesextend in the direction perpendicular to the source-channel-draindirection (i.e., the word lines extend perpendicular to the chargecarrier flow direction). The TFT EEPROMs do not contain a separatecontrol gate. Instead, the word line acts as a control gate in regionswhere it overlies the floating gates.

The layout of Koyama requires two polycide contact pads to be formed tocontact the source and drain regions of each TFT. The bit lines areformed above the word lines and contact the contact pads through contactvias in an interlayer insulating layer which separates the bits linesfrom the word lines. Therefore, each cell in this layout is not fullyself-aligned, because the contact pads and the contact vias are eachpatterned using a non-self aligned photolithography step. Therefore,each memory cell has an area that is larger than desirable, and leads toa less than optimum cell density. The memory cell of Koyama is alsocomplex to fabricate because it requires the formation of contact padsand bit line contact vias. Furthermore, the manufacturability of thedevice of Koyama is less than optimum because both bit lines and wordlines have a non-planar top surface due to the non-planar underlyingtopography. This may lead to open circuits in the bit and word lines.

The Virtual Ground Array approach to crystalline silicon non-volatilememories has also been known for some time and is an elegant way ofaggressively reducing memory cell size. Turning now to FIG. 99, thebasic approach utilizes a cross point array 5610 of bitlines in buriedn+ diffusion 5612 within a single crystalline silicon p-type substrate5614 and wordlines formed of polysilicon rails 5616 disposed over thesubstrate 5614. A transistor is formed from adjacent bitlines 5612 and ap-type channel region 5618 disposed between the adjacent bitlines 5612.A layer of gate oxide 5620 insulates the floating gates 5622, which lieabove the channels 5618 and are formed of, for example, polysilicon. Anupper dielectric layer 5624 insulates the floating gates 5622 frompolysilicon wordlines (WLs) 5616.

“Virtual Ground” refers to the fact that there is no dedicated groundline in the array. Whenever a cell is chosen for read or program, a pairof buried n+ bitlines (BLs) is the source and drain with the sourcegrounded. For example, to select the cell 5624 outlined in FIG. 100,BL(k) and BL(k+1) would be selected as the source and drain (or viceversa) and WL(j) would be selected as the control gate of the device. Inone approach, all of the bit lines to the left of BL(k) as shown in FIG.100 would be held at the same potential as BL(k) and all of the bitlines to the right of BL(k+1) would be held at the same potential asBL(k+1) so that source-drain current would only flow (for read andprogramming) in the selected cell (all other WLs being grounded).

In all of these approaches, the charge storage medium is a conductingfloating gate made of doped polysilicon. By hot electron injectionprogramming (the method of choice in all classic EPROM (erasableprogrammable read only memory) and single transistor Flash memorycells), electrons are injected onto the floating gate thus changing thethreshold voltage of the inherent MOS transistor.

The above discussed SONOS (polysilicon-blocking oxide-nitride-tunneloxide-silicon) charge trapping approach has reemerged as a viablecandidate for non-volatile MTP memories arranged in a virtual groundarray structure 5626, as shown in FIG. 101. The array includes n+ buriedbitlines 5612 disposed in a single crystalline silicon substrate 5614.An ONO (oxide-nitride-oxide) dielectric stack 5628 insulates bitlines5612 from polysilicon wordline 5630. The hot electrons are injected intothe ONO dielectric stack 5628 near the drain edge during programmingwhere charge is trapped in the nitride layer. Two bits can be stored permemory cell utilizing this approach because hot electrons are injectedinto the ONO dielectric stack at the programming drain edge. Since thenitride charge storage medium does not laterally conduct, the chargestays where it was injected. Trapped charge near the source of atransistor has a large effect on the transistor's threshold voltagewhile trapped charge near the drain has little effect on thresholdvoltage. Accordingly, individual charge zones on either side of the ONOlayer may be written and read by simply reversing the drain and sourceconnections for the cell. When the cell is programmed, charge isinjected at the zone closest to the drain. If source and drain arereversed for the same cell, another charge may be injected into the samecell but at the “other” drain. Both sides can also be read, thus twobits per cell may be stored and retrieved.

The above described prior art devices are relatively expensive becausetheir density is not optimized.

SUMMARY OF THE INVENTION

According to one preferred embodiment of the present invention, asemiconductor device comprises a monolithic three dimensional array ofcharge storage devices comprising a plurality of device levels, whereinat least one surface between two successive device levels is planarizedby chemical mechanical polishing.

In another preferred embodiment of the present invention, a monolithicthree dimensional array of charge storage devices is formed in anamorphous or polycrystalline semiconductor layer over a monocrystallinesemiconductor substrate, and driver circuitry is formed in the substrateat least in part under the array, within the array or above the array.

Another preferred embodiment of the present invention provides a memorydevice comprising a first input/output conductor formed above or on afirst plane of a substrate. The memory device also includes a secondinput/output conductor. A semiconductor region is located between thefirst input/output conductor and the second input/output conductor at anintersection of their projections. The memory device includes a chargestorage medium wherein charge stored in the charge storage mediumaffects the amount of current that flows between the first input/outputconductor and the second input/output conductor.

Another preferred embodiment of the present invention provides anonvolatile read-write memory cell having an N doped region, a P dopedregion, and a storage element disposed between the two.

Another preferred embodiment of the present invention provides a methodfor operating a memory cell. The method comprises the steps of trappingcharge in a region to program the cell, and passing current through theregion when reading data from the cell.

Another preferred embodiment of the present invention provides an arrayof memory cells, said array having a plurality of memory cells eachcomprising at least one semiconductor region and a storage means fortrapping charge. The array also has control means for controlling theflow of current through the semiconductor region and the storage meansof the cells.

Another preferred embodiment of the present invention provides anonvolatile stackable pillar memory device and its method offabrication. The memory device includes a substrate having a firstplane. A first contact is formed on or above the plane of a substrate. Abody is formed on the first contact. A second contact is formed on thebody wherein the second contact is at least partially aligned over thefirst contact. A control gate is formed adjacent to the charge storagemedium. A read current flows between the first contact and the secondcontact in a direction perpendicular to the plane of the substrate.

Another preferred embodiment of the present invention provides a fieldeffect transistor, comprising a source, a drain, a channel, a gate, atleast one insulating layer between the gate and the channel, and a gateline which extends substantially parallel to a source-channel-draindirection and which contacts the gate and is self aligned to the gate.

Another preferred embodiment of the present invention provides a threedimensional nonvolatile memory array, comprising a plurality ofvertically separated device levels, each level comprising an array ofTFT EEPROMs, each TFT EEPROM comprising a channel, source and drainregions, and a charge storage region adjacent to the channel, aplurality of bit line columns in each device level, each bit linecontacting the source or the drain regions of the TFT EEPROMs, aplurality of word line rows in each device level, and at least oneinterlayer insulating layer located between the device levels.

Another preferred embodiment of the present invention provides an EEPROMcomprising a channel, a source, a drain, a tunneling dielectric locatedabove the channel, a floating gate located above the tunnelingdielectric, sidewall spacers located adjacent to the floating gatesidewalls, a word line located above the floating gate, and a controlgate dielectric located between the control gate and the floating gate.The control gate dielectric is located above the sidewall spacers.

Another preferred embodiment of the present invention provides an arrayof nonvolatile memory cells, wherein each memory cell comprises asemiconductor device and each memory cell size per bit is about (2F²)/N,where F is a minimum feature size and N is a number of device layers inthe third dimension, and where N>1 Another preferred embodiment of thepresent invention provides a method of making an EEPROM, comprisingproviding a semiconductor active area, forming a charge storage regionover the active area, forming a conductive gate layer over the chargestorage region and patterning the gate layer to form a control gateoverlying the charge storage region. The method also comprises dopingthe active area using the control gate as a mask to form source anddrain regions in the active area, forming a first insulating layer aboveand adjacent to the control gate, exposing a top portion of the controlgate without photolithographic masking, and forming a word linecontacting the exposed top portion of the control gate, such that theword line is self aligned to the control gate.

Another preferred embodiment of the present invention provides a methodof making an EEPROM, comprising providing a semiconductor active area,forming a tunnel dielectric layer over the active area, forming aconductive gate layer over the tunnel dielectric layer, patterning thegate layer to form a floating gate overlying the tunnel dielectric layerand doping the active area using the floating gate as a mask to formsource and drain regions in the active area. The method also comprisesforming sidewall spacers adjacent to the floating gate sidewalls,forming a first insulating layer above and adjacent to the sidewallspacers and above the source and drain regions, forming a control gatedielectric layer over the floating gate, and forming a word line overthe control gate dielectric and over the first insulating layer.

Another preferred embodiment of the present invention provides a methodof forming a nonvolatile memory array, comprising forming asemiconductor active layer, forming a first insulating layer over theactive layer, forming a plurality of gate electrodes over the firstinsulating layer and doping the active layer using the gate electrodesas a mask to form a plurality of source and drain regions in the activelayer, and a plurality of bit lines extending substantiallyperpendicular to a source-drain direction. The method also comprisesforming a second insulating layer above and adjacent to the gateelectrodes and above the source regions, drain regions and the bitlines, planarizing the second insulating layer, and forming a pluralityof word lines over the second insulating layer extending substantiallyparallel to the source-drain direction.

Another preferred embodiment of the present invention provides a methodof making an EEPROM array, comprising providing a semiconductor activearea, forming a plurality of dummy blocks above the active area, dopingthe active area using the dummy blocks as a mask to form source anddrain regions in the active area, forming an intergate insulating layerabove and between the dummy blocks, planarizing the intergate insulatinglayer to expose top portions of the dummy blocks, selectively removingthe dummy blocks from between portions of the planarized intergateinsulating layer to form a plurality of vias between the portions of theintergate insulating layer, forming charge storage regions over theactive area in the plurality of vias, forming a conductive gate layerover the charge storage regions, and patterning the conductive gatelayer to form a control gate overlying the charge storage region.

Another preferred embodiment of the present invention provides a methodof forming a TFT EEPROM, comprising forming a TFT EEPROM comprising anamorphous silicon or a polysilicon active layer, a charge storage regionand a control gate, providing a crystallization catalyst in contact withthe active layer, and heating the active layer after the step ofproviding the catalyst to recrystallize the active layer using thecatalyst.

Another preferred embodiment of the present invention provides a two- orthree-dimensional memory array constructed of thin film transistorsdisposed above the substrate. Spaced-apart conductors disposed in afirst direction form contacts with memory cells formed in rail stacksdisposed in a second direction different from the first direction. Alocal charge trapping medium receives and stores hot electrons injectedby thin film transistors formed at the intersections of the spaced-apartconductors and the rail stacks. The local charge trapping medium may beused to store charge adjacent to a transistor drain and by reversing thedrain and source lines, two bits per memory cell may be stored, ifdesired. A programming method insures that stored memory will not beinadvertently disturbed.

Another preferred embodiment of the present invention provides anon-volatile thin film transistor (TFT) memory device that isconstructed above a substrate. It employs a source, drain and channelformed of transition metal crystallized silicon. A local charge storagefilm is disposed vertically adjacent to the channel and stores injectedcharge. A two- or three-dimensional array of such devices may beconstructed above the substrate. Spaced-apart conductors disposed in afirst direction form contacts with memory cells formed in rail stacksdisposed in a second direction different from the first direction. Thelocal charge storage film receives and stores charge injected by TFTsformed at the intersections of the spaced-apart conductors and the railstacks. The local charge storage film may be used to store chargeadjacent to a transistor drain and by reversing the drain and sourcelines, two bits per memory cell may be stored, if desired. A programmingmethod insures that stored memory will not be inadvertently disturbed.

Another preferred embodiment of the present invention provides a flashmemory array disposed above a substrate, the array comprising a firstplurality of spaced-apart conductive bit lines disposed at a firstheight above the substrate in a first direction, and a second pluralityof spaced-apart rail-stacks disposed at a second height in a seconddirection different from the first direction, each rail-stack includinga plurality of semiconductor islands whose first surface is in contactwith said first plurality of spaced-apart conductive bit lines, aconductive word line, and charge storage regions disposed between asecond surface of the semiconductor islands and the word line.

Another preferred embodiment of the present invention provides a TFTCMOS device, comprising a gate electrode, a first insulating layeradjacent to a first side of the gate electrode, a first semiconductorlayer having a first conductivity type disposed on a side of the firstinsulating layer opposite to the gate electrode, a first source anddrain regions of a second conductivity type disposed in the firstsemiconductor layer, first source and drain electrodes in contact withthe first source and drain regions and disposed on a side of the firstsemiconductor layer opposite to the first insulating layer. The TFT CMOSdevice further comprises a second insulating layer adjacent to a secondside of the gate electrode, a second semiconductor layer having a secondconductivity type disposed on a side of the second insulating layeropposite to the gate electrode, second source and drain regions of afirst conductivity type disposed in the second semiconductor layer, andsecond source and drain electrodes in contact with the second source anddrain regions and disposed on a side of the second semiconductor layeropposite to the second insulating layer.

Another preferred embodiment of the present invention provides a circuitcomprising a plurality of charge storage devices and a plurality ofantifuse devices.

Another preferred embodiment of the present invention provides asemiconductor device comprising a semiconductor active region, a chargestorage region adjacent to the semiconductor active region, a firstelectrode, and a second electrode. Charge is stored in the chargestorage region when a first programming voltage is applied between thefirst and the second electrodes, and a conductive link is formed throughthe charge storage region to form a conductive path between the firstand the second electrodes when a second programming voltage higher thanthe first voltage is applied between the first and the secondelectrodes.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is an illustration of a pillar memory in accordance with anembodiment of the present invention.

FIG. 1B is an illustration of an overhead view of a pillar memory inaccordance with an embodiment of the present invention having a singlecharge storage medium and single control gate surrounding a pillar.

FIG. 1C is an illustration of an overhead view showing a pillar memoryin accordance with an embodiment of the present invention havingmultiple charge storage mediums and multiple control gates.

FIG. 2 is an illustration of the pillar memory in accordance with anembodiment of the present invention.

FIGS. 3A-3D illustrate an ultra thin channel pillar memory device inaccordance with an embodiment of the present invention and its method offabrication.

FIG. 4 is an illustration of a pillar memory of an embodiment of thepresent invention having Schottky contacts.

FIG. 5 is an illustration of a gated diode pillar memory in accordancewith an embodiment of the present invention.

FIG. 6 is an illustration of a pillar memory in accordance with anembodiment of the present invention having a nanocrystal floating gate.

FIG. 7 is an illustration of a pillar memory of an embodiment of thepresent invention having a charge trapping dielectric.

FIGS. 8A and 8B illustrate a method of forming a pillar utilizing anexplicit pillar formation process.

FIGS. 9A and 9B illustrate a method of forming a pillar utilizing anintersection etch technique.

FIGS. 10A-10E illustrate a method of forming a pillar memory device inaccordance with an embodiment of the present invention utilizing a“spacer etch” technique.

FIGS. 11A-11C illustrate a method of forming a common control gatebetween adjacent pillar memories as well as showing the isolation ofcontrol gates between adjacent pillars.

FIGS. 12A and 12B illustrate a method of forming a common continuousfilm control gate between two or more levels of pillar memories.

FIGS. 13 to FIG. 28 illustrate a method of fabricating multiple levelsof pillar memories in accordance with an embodiment of the presentinvention.

FIG. 29A is a representation of a memory cell of an embodiment of thepresent invention.

FIG. 29B is a graph illustrating the characteristics of the cell of FIG.29A.

FIG. 30 is a cross-sectional elevation view of a two terminal cell builtin accordance with an embodiment of the present invention.

FIG. 31 is a cross-sectional elevation view of a three terminal cellbuilt in accordance with an embodiment of the present invention.

FIG. 32 is a cross-sectional elevation view of a three-dimensionalmemory array employing rail stacks built in accordance with anembodiment of the present invention.

FIG. 33 is a perspective view of a cell formed as a pillar above asubstrate in accordance with an embodiment of the present invention.

FIG. 34 is another embodiment of a cell formed as a pillar.

FIGS. 35 and 36 are schematics of a three dimensional array of devices.

FIG. 37 is a side cross-sectional view of a wafer after ONO dielectric,first gate electrode, protective oxide and blocking nitride layers havebeen deposited in a method according to an embodiment of the presentinvention.

FIG. 38 is a side cross-sectional view of a memory array after bit linepatterning and source/drain implantation. The cross-section isperpendicular to the bit lines.

FIG. 39 is a side cross-sectional view of the array after salicideprocess. The cross-section is perpendicular to the bit lines.

FIG. 40 is a side cross-sectional view of the array after the oxide filland planarization. The cross-section is perpendicular to the bit lines.

FIG. 41 is a side cross-sectional view of the array after the blockinglayer is removed. The cross section is perpendicular to the bit lines.

FIG. 42 is a side cross-sectional view of the array during word lineformation. The cross-section is perpendicular to the bit lines.

FIG. 43 is a side cross-sectional view of the array after word lineformation along line A-A in FIG. 42. The cross-section is perpendicularto the word lines and passes through a bit line.

FIG. 44 is a side cross-sectional view of the array after word lineformation along line B-B in FIG. 42. The cross-section is perpendicularto the word lines and passes through a transistor channel.

FIG. 45 is a side cross-sectional view of the array of the secondpreferred embodiment after the oxide fill and planarization. Thecross-section is perpendicular to the bit lines.

FIG. 46 is a side cross-sectional view of the array of the secondpreferred embodiment after word line formation. The cross-section isperpendicular to the bit lines.

FIG. 47 is a side cross-sectional view of the array of a preferredembodiment after word line formation. The cross-section is perpendicularto the bit lines.

FIGS. 48A-C and 49A-C illustrate alternative methods of making a TFT ofthe array of a preferred embodiment.

FIGS. 50 and 51 are side cross-sectional views of the array of twopreferred aspects of a preferred embodiment after word line formation.The cross-section is perpendicular to the bit lines.

FIG. 52 is a three dimensional view of a three dimensional array of apreferred embodiment.

FIG. 53 is a side cross-sectional view of a word line contact conductorand bit line contact conductor at the same level. Openings are made forthe next level contacts.

FIG. 54 is a side cross-section view of a word line contact conductor inlevel N+1 and word line and bit line contact conductors in level N.Landing pads are made in level N+1 conductor for the next levelcontacts.

FIGS. 55-61 are side cross-sectional views of a method of making thearray of a preferred embodiment. The cross-section is perpendicular tothe bit lines.

FIG. 62 is a top view of the array of a preferred embodiment of thepresent invention after forming crystallization windows.

FIGS. 63 and 64 are side cross-sectional views along lines A-A and B-B,respectively, in FIG. 62. The cross-section is perpendicular to the bitlines in FIG. 63 and parallel to the bit lines in FIG. 64.

FIG. 65 is a top view of the array of a preferred embodiment after thecrystallization of the active layer.

FIG. 66 is a drawing showing a front perspective view of atwo-dimensional memory array in accordance with a specific embodiment ofthe present invention.

FIG. 67 is a drawing showing an elevational cross sectional view of atwo-dimensional memory array in accordance with a specific embodiment ofthe present invention.

FIG. 68 is a drawing showing a top plan view of a memory array inaccordance with a specific embodiment of the present invention.

FIG. 69 is a drawing showing an elevational cross sectional view of athree-dimensional memory array in accordance with a specific embodimentof the present invention.

FIG. 70 is a drawing showing an elevational cross sectional view of atwo-dimensional memory array in accordance with a specific embodiment ofthe present invention.

FIG. 71 is a drawing showing an elevational cross sectional view of athree-dimensional memory array in accordance with a specific embodimentof the present invention.

FIG. 72 is a drawing showing an elevational cross sectional view of amemory array in accordance with a specific embodiment of the presentinvention.

FIG. 73 is a drawing showing an elevational cross sectional view of athree-dimensional memory array in accordance with a specific embodimentof the present invention.

FIGS. 74 and 75 are drawings illustrating methods for programming memorycells in accordance with a specific embodiment of the present invention.

FIG. 76 is a drawing illustrating a method of fabrication of memorycells in accordance with a specific embodiment of the present invention.

FIG. 77 is a cross sectional drawing illustrating a SONOS on adielectric stack.

FIG. 78 is a cross-sectional drawing illustrating a nanocrystallinecharge storage medium.

FIG. 79 is a cross-sectional drawing of a bitline of doped polysiliconhaving a refractory metal silicide formed therein to improve lateralconductivity.

FIG. 80 is a cross-sectional drawing of a substrate in accordance with aspecific embodiment of the present invention.

FIGS. 81A-81H illustrate steps in the fabrication of a memory array inaccordance with a specific embodiment of the present invention.

FIGS. 82A-821 illustrate steps in the fabrication of a memory array inaccordance with a specific embodiment of the present invention.

FIGS. 83-85 illustrate flash memory arrays according to a preferredembodiment of the present invention.

FIGS. 86A-86J illustrate methods of making the arrays of FIGS. 83-85.

FIG. 87 illustrates a CMOS array according to a preferred embodiment ofthe present invention.

FIGS. 88A-D illustrate a method of making the CMOS array of FIG. 87.

FIGS. 89-92 illustrate logic and memory circuits using the CMOS array ofFIG. 87.

FIG. 93 is a process flow diagram illustrating a process for fabricatinga crystallized amorphous silicon layer for use in a non-volatile TFTmemory device in accordance with a specific embodiment of the presentinvention.

FIGS. 94A-94H are vertical cross-sectional drawings illustrating stepsin the process of FIG. 93.

FIG. 95 is a top plan view of a portion of a silicon wafer afterprocessing in accordance with the process of FIG. 93.

FIGS. 96-101 are illustrations of prior art devices.

DETAILED DESCRIPT10N OF THE PREFERRED EMBODIMENTS

The present inventors have realized that the cost of memory and logicdevices would be decreased if the device density was increased. Thus,the present inventors have provided an ultra dense matrix array ofcharge storage semiconductor devices which has an increased density anda lower cost.

One method of improving device density is to arrange the devices in amonolithic three dimensional array of charge storage devices comprisinga plurality of device levels.

The term “monolithic” means that layers of each level of the array weredirectly deposited on the layers of each underlying level of the array.In contrast, two dimensional arrays may be formed separately and thenpackaged together to form a non-monolithic memory device.

In order to form such a three dimensional array, especially an arrayhaving four or more layers, at least one surface between two successivedevice levels is planarized by chemical mechanical polishing (CMP). Incontrast to other planarization methods, such as etch back, chemicalmechanical polishing allows a sufficient degree of planarization tostack multiple device levels of a commercially feasible device on top ofeach other. The inventors have found that chemical mechanical polishingtypically achieves flatness on the order of 4000 Angstroms or lesswithin a stepper field (i.e., a peak to peak roughness value of 4000Angstroms or less in an area on the order of 10 to 50 mm) inthree-dimensional memory arrays, even after 4 to 8 layers of the arrayhave been formed. Preferably, the peak to peak roughness of a layer inthe array polished by CMP is 3000 Angstroms or less, such as 500 to 1000Angstroms, within a stepper field. In contrast, etch back alonetypically does not afford sufficient flatness to achieve a commerciallysuitable three-dimensional memory or logic monolithic array.

For example, the term “at least one surface between two successivedevice levels is planarized by chemical mechanical polishing” includessurfaces formed in the bottom and intermediate device layers, as well assurfaces of the interlayer insulating layers that are disposed inbetween the device layers. Thus, the surfaces of conductive and/orinsulating layers in each intermediate and bottom device level of thearray are planarized by chemical mechanical polishing. Thus, if thearray includes at least four device levels, then at least three devicelevels should have at least one surface that is planarized by chemicalmechanical polishing. The surfaces of the conductive and/or insulatinglayers in the top device level may also be planarized by chemicalmechanical polishing.

Another method of improving device density is to vertically integratethe driver or peripheral circuits with the memory or logic array. In theprior art, the peripheral circuits were formed in the periphery of themonocrystalline silicon substrate, while the memory or logic array wasformed in the other portions of the substrate, adjacent to theperipheral circuits. Thus, the peripheral circuits occupied valuablesubstrate space in the prior art devices. In contrast, a preferredembodiment of the present invention provides a monolithic threedimensional array of charge storage devices formed in an amorphous orpolycrystalline semiconductor layer over a monocrystalline semiconductorsubstrate, while at least part, and preferably all, the driver (i.e.,peripheral) circuitry is formed in the substrate under the array, withinthe array or above the array. Preferably, the driver circuitry comprisesat least one of sense amps and charge pumps formed wholly or partiallyunder the array in the substrate.

FIG. 35 schematically illustrates an array of charge storage logic ormemory devices 3101 formed above an interlayer insulating layer 3102disposed above a monocrystalline substrate 3105. The array of chargestorage logic or memory devices 3101 are thus arranged as a threedimensional monolithic array thin film transistors or diodes inamorphous or polysilicon layers. The array 3101 has a plurality ofdevice levels 3104, preferably separated by interlayer insulatinglayers. The driver circuits 3103, such as sense amps and charge pumps,are disposed in the monocrystalline substrate 3105, as CMOS or othertransistors. FIG. 36 schematically illustrates an array of chargestorage logic or memory devices 3101 formed above a monocrystallinesubstrate 3105 as thin film transistors or diodes in amorphous orpolysilicon layers. The driver circuits 3103, such as sense amps andcharge pumps, are formed within the array 3101 and/or above the array3101.

Another method of improving device density is self-alignment and usingthe same photolithography step to pattern different layers. The devicecell area is enlarged by misalignment tolerances that are put into placeto guarantee complete overlap between features on different layers.Thus, the present inventors have developed a fully or partially alignedmemory cell structure that does not require misalignment tolerances orthat requires a reduced number of misalignment tolerances. In such acell structure, certain device features may be self aligned to otherdevice features, and do not require a photolithography step forpatterning. Alternatively, plural layers may be etched using the samephotoresist mask or a lower device layer may be etched using a patternedupper device layer as a mask. Particular examples of aligned memorycells will be discussed in more detail below.

The charge storage devices of the array may be any type of semiconductordevices which store charge, such as EPROMs or EEPROMs. In the preferredembodiments of the present invention described in detail below, thecharge storage devices are formed in various configurations, such as apillar TFT EEPROM, a pillar diode with a charge storage region, a selfaligned TFT EEPROM, a rail stack TFT EEPROM, and various otherconfigurations. Each of these configurations provides devices with ahigh degree of planarity and alignment or self-alignment to increase thearray density.

For example, in the pillar TFT EEPROM or a pillar diode with a chargestorage region, at least one side of the semiconductor active region isaligned to one of the electrodes contacting the semiconductor activeregion. Thus, in a pillar TFT EEPROM configuration, the semiconductoractive region is aligned to both the source and the drain electrodes.This alignment occurs because at least two sides of the activesemiconductor region and one of the electrodes are patterned during asame photolithography step (i.e., etched using the same photoresist maskor one layer is used as a mask for the other layer).

In a self-aligned TFT, two sides of the active semiconductor region arealigned to a side of the gate electrode only in the channel portion ofthe active semiconductor region, but not in the source and drainregions. This alignment occurs because at least two sides of the channelregion and the gate electrode are patterned during a samephotolithography step (i.e., etched using the same photoresist mask orone layer is used as a mask for the other layer). In contrast, thesource and drain regions are not etched.

In the following description, numerous specific details are set forthsuch as specific thicknesses, materials etc. in order to provide athorough understanding of the present invention. It will be apparent toone skilled in the art that the present invention may be practicedwithout these specific details. In other instances, well-known concepts,circuit and fabrication techniques are not set forth in detail in ordernot to unnecessarily obscure the present invention.

Any feature of any embodiment described below may be used in anotherembodiment. The first set of embodiments describes various pillardevices, the second set of embodiments describes self-aligned TFTdevices and the third set of embodiments describes rail stack TFTdevices. The fourth and fifth set of embodiments describes how thesedevices may be used in a logic or memory circuit. The final set ofembodiments describes the use of metal induced crystallization toimprove the crystallinity of the device levels.

I. The Pillar Devices

The present embodiment is directed to thin film transistors (TFTs) anddiodes arranged in a pillar configuration (i.e., the vertical directionwith respect to the substrate, where the length of the device isperpendicular to the substrate) and their method of fabrication.Preferably, the pillar devices form a charge trapping memory that has avertical read current. The memory includes a first input/outputconductor formed on or above a plane of a substrate and a secondinput/output conductor located above and spaced apart from the firstinput/output conductor. The first input/output conductor and the secondinput/output conductor are positioned so that they overlap or intersectone another and preferably intersect perpendicular to one another. Asemiconductor region, such as a doped silicon region, is formed betweenthe first input/output conductor and the second input/output conductorat the intersection of the first input/output conductor and the secondinput/output conductor. A charge storage medium, such as but not limitedto a charge trapping dielectric, is formed near the semiconductor regionand affects the amount of current that flows through the semiconductorregion between the first input/output conductor and the secondinput/output conductor for a given voltage applied across the firstinput/output conductor and the second input/output conductor. The amountof current (read current) for a single voltage that flows through thesemiconductor region can be used to determine whether or not charge isstored in the charge storage medium and therefore whether or not thememory is programmed or erased. The read current that flows through thesemiconductor region between the first input/output conductor and thesecond input/output conductor flows in a direction perpendicular to theplane of the substrate in which or on which the memory is formed. Thestructure of the charge trapping memory of the present embodiment, aswell as its method of fabrication, is ideally suited for integrationinto a three dimensional array of memory devices.

As will be discussed below, the charge trapping memory device of thepresent embodiment can be fabricated with one of two general structures.In one embodiment the charge storage medium is formed adjacent to thesemiconductor region and in a second embodiment the charge storagemedium is formed above or below the semiconductor region.

1. A Three Terminal Pillar Memory with Adjacent Charge Storage Medium

An embodiment of the present invention is a three terminal nonvolatilestackable pillar memory device. A pillar memory device 100 in accordancewith this embodiment of the present invention is broadly illustrated inFIG. 1A. Pillar memory device 100 includes a first contact region 102formed on a first input/output (I/O) 103 conductor formed on or above aplane (x-y) of a single crystal substrate 101. A semiconductor body 104is formed directly on the first contact region 102 and a second contactregion 106 is formed directly on the body 104. A second I/O conductor116 is formed on the second contact region 106. The first contact region102, the body 104, and the second contact (source/drain) region 106 areeach vertically aligned with one another to form a pillar 108. Adjacentto and in contact with body 104 is a charge storage medium 110. Acontrol gate 112 is formed adjacent to and in direct contact with thecharge storage medium 110. The control gate 112 and charge storagemedium 110 are constructed so that they lie laterally adjacent to pillar108 so that they may electrically communicate with pillar 108. Thecharge storage medium is the region that electrically screens thecontrol gate and the channel region addressed by the control gate.

The programmed or unprogrammed state of the pillar memory device isdetermined by whether or not charge is stored in charge storage medium110. The charge stored in the charge storage medium adds or subtractsfrom the voltage applied to the control gate, thereby altering thevoltage required to form a conducting channel in body 104 to enable acurrent (e.g., read current IR) to flow between the first and secondcontact (source/drain) regions. This voltage is defined as the VT. Theamount of voltage required to form a conducting channel in body 104 orthe amount of current flowing in the body for a given control gatevoltage can be used to determine whether or not the device is programmedor unprogrammed. Additionally, multiple bits of data can be stored in asingle charge storage medium 110 whereby each different amount of storedcharge creates a different VT each representing a different state of thecharge storage medium. Because the charge storage medium can containmultiple states, multiple bits can be stored in a single charge storagemedium.

During read operations of device 100, when a conductive channel isformed in body 104, current 114 flows vertically (z) (or perpendicular)with respect to the plane (x-y) of the substrate 101 above which pillarmemory device is formed. By creating a memory device with a “vertical”read current path, the pillar memory cell of the present invention canbe easily stacked in a three dimensional array with source/drainconductors 103 and 116 running parallel or perpendicular to each otherand parallel to the plane of the substrate 101 without requiring the useof vertical interconnect strategies for the source and drainconnections. The conductor 112 to the control gate may be run vertically(as shown in FIG. 1A) or horizontally.

Although memory device 100 shown in FIG. 1A includes a charge storagemedium 110 and a control gate 112 formed on only one side or surface ofpillar 108, it is to be appreciated that the pillar memory device of thepresent invention can be fabricated so that the entire body 110 of thepillar 108 is surrounded by a single charge storage member 110 and asingle control gate 112 as shown in FIG. 1B. Additionally, each surfaceof the pillar 108 can have an independently controlled charge storagemember and control gate as shown in FIG. 1C and thereby enable multiplebits of data to be stored in a single pillar memory device of thepresent invention. The use of multiple charge storage members andcontrol gates enables the storage of multiple values on a single pillardevice by determining how much of the channel is exposed to charge.Additionally, each face of body 104 of pillar 108 can have differentdoping densities to create different threshold voltages for each face tofurther enable the pillar memory to store additional states andtherefore additional bits.

FIG. 2 shows an embodiment of the present invention where the pillar 207comprises a first source/drain contact region 202 comprising a heavilydoped N+ silicon film having a doping density in the range between1×10¹⁹ to 1×10²⁰, preferably 1×10¹⁹ to 1×10²¹ atoms/cm³, formed on afirst input/output 204 (e.g. bit line) formed on or above a substrate201. A body comprising a lightly doped P− type silicon film 206 having adoping density between 1×10¹⁶ to 1×10¹⁸ atoms/cm³ is formed on and indirect contact with the first N+ source/drain contact region 202. Asecond source/drain region 208 comprising a heavily doped N+ siliconfilm having a doping density of 1×10¹⁹ to 1×10²⁰, preferably 1×10¹⁹ to1×10²¹, atoms/cm³ is formed on and in direct contact with P type siliconfilm 206, as shown in FIG. 2. A second conductive input/output (e.g.word line/bit line) 210 is formed on the second N+ source/drain region208. The N+ source/drain films 202 and 208 can have a thickness between500-1000 Å. The first and second input/outputs 204 and 210 can be formedof a highly conductive material such as but not limited to a metal suchas tungsten, a silicide such as titanium silicide or tungsten siticide,or heavily doped silicon. In memory device 200 N+ source/drain region202, P type silicon body 206 and N+ source/drain region 208 are eachsubstantially vertically aligned with one another to form pillar 207.

Pillar memory 200, shown in FIG. 2, has a charge storage medium 211comprising a tunnel dielectric 212, a floating gate 214, and a controlgate dielectric 216. The tunnel dielectric is formed adjacent to and indirect contact with P type silicon body 206. A floating gate 214 isformed adjacent to and in direct contact with tunnel dielectric 212.Floating gate 214 comprises a conductor such as but not limited to dopedsilicon, such as N type silicon, or metal such as tungsten. The controlgate dielectric 216 is formed adjacent to and in direct contact withfloating gate 214. Finally a control gate 218 is formed adjacent to andin direct contact with control gate dielectric 216. Control gate 218 isformed of a conductor such as but not limited to doped silicon or ametal such as tungsten.

The thicknesses of P type silicon film 206 and tunnel dielectric 212 aredependent upon the desired programming and erasing voltage. If lowvoltage programming operations between 4 to 5 volts are desired, thenP-type silicon film 206 can have a thickness between 1000-2500 Å and thetunnel dielectric can have a thickness between 20 and 150 Å, such as20-50 Å, preferably 80-130 Å. (If a nitride tunnel dielectric 212 isdesired it would be scaled slightly thicker.) It is to be appreciatedthat the thickness of P− type silicon film 206 defines the channellength of the device. If higher voltage (6-10 volts) programmingoperations are desired the P type silicon film 206 can have a thicknessbetween 6000-7000 Å and tunnel dielectric 212 can have a thicknessbetween 60-100 Å. The control dielectric 216 typically has a thicknesson order of tunnel dielectric 212 but is slightly (10-30 Å) thicker,preferably 130 to 180 Å.

Pillar memory 200 is considered programmed or unprogrammed dependingupon 25 whether or not charge is stored on floating gate 214. Pillarmemory device 200 can be programmed utilizing drain side programmingwhereby electrons are placed on floating gate 214 by grounding thesource region 202 while a relatively high voltage is applied to thedrain region 208 and while approximately 4-5 volts, for low voltageoperations, or 6-10 volts, for high voltage operations, is applied tocontrol gate 218 in order to invert a portion of P− type silicon region206 into N type silicon so that a channel region is formed and electronsflow between the source region and the drain region. The high controlgate voltage pulls electrons from the inverted channel region throughthe tunnel dielectric 212 and on to floating gate 214. Because electronslose some of their energy tunneling through the tunnel oxide, they nolonger have enough energy to escape from the floating gate which issurrounded by insulators. Other techniques such as but not limited tosource side injection can be used to program memory device 200.

Memory device 200 can be erased by removing stored electrons fromfloating gate 214. Memory device 200 can be erased by placing arelatively high positive voltage (3 volts) on to the source region,while applying a negative voltage of approximately 4-5 volts in lowvoltage operations or 6-10 volts for high voltage operations on tocontrol gate 218. The positive voltage on the source region attractselectrons on floating gate 214 and thereby pulls electrons off floatinggate 214 through tunnel dielectric 212 and into the source region.

In order to read the state of memory device 200, a voltage (such as 3.3volts) can be applied to the drain while a given control gate voltage isapplied to the control gate. The amount of current (read current) thatflows from the drain region through the channel region and into thesource region for a given control gate voltage can be used to determinethe state of the memory device. Alternatively, one can read the state ofmemory 200 by sensing the amount of control gate voltage necessary tocause a given read current to flow through body 206. When read currentflows between the first and second source/drain regions 202 and 208through body 206 it flows in a direction perpendicular (z) to the plane(x-y) of the substrate 201 on or above which it is built.

FIG. 3 shows another embodiment of the nonvolatile pillar memory deviceof the present invention. FIG. 3 shows a three terminal nonvolatilepillar memory device 300 having an ultra thin silicon channel or body302. Like memory device 200 the ultra thin memory device 300 has a firstN+ source/drain contact region 202 formed on a first input/output 204.An insulator 304, such as an SiO₂ film or a silicon nitride film, isformed on the first source/drain contact region 202. A second N+source/drain region 208 is formed on the insulating layer 304. Insulator304 separates the source/drain regions 202 and 208 from one another andtherefore defines the channel length of the device. A 30 thin P− typesilicon film 302 having a concentration in the range between 1×10¹⁶ to1×10¹⁸ atoms/cm³ is formed along the sidewalls of the N+/insulator/N+stack so that it is adjacent to and in direct contact with the first andsecond source/drain regions as well as separating insulator 304. The P−type silicon film acts as the channel or body for the device and bridgesthe gap between source/drain regions 202 and 208. By forming a thin P−type silicon film adjacent to the N+/insulator/N+ stack the channelregion can be made extremely thin, between 50-100 Å. The thickness ofthe P− type silicon film which represents the channel thickness ispreferably less than ½ the channel length (i.e. the distance between thesource/drain regions 202 and 208) and ideally less than ⅓ the channellength.

Like memory device 200, memory device 300 also includes a charge storagemedium 211, and a control gate 218. When transistor 300 is turned on, aportion of the P− type silicon region inverts to form a conductivechannel therein so that current can flow from one source/drain region202 to the other source/drain region 208. The majority of the currentpath 306 through the ultra thin body 302 or channel from onesource/drain region to the other source/drain region is in a directionperpendicular (z) to the plane (x-y) of the substrate above which thedevice is built.

An ultra thin channel or body transistor can be formed, for example, byusing a “spacer etch” technique. For example, as shown in FIG. 3B an N+silicon/insulator/N+ silicon stack can be blanket deposited over asubstrate having a patterned metal I/O 204. The stack is then patternedutilizing well-known photolithography and etching techniques into apillar 306 is shown in FIG. 3B. A P− type silicon film can then beblanket deposited over the pillar as shown in FIG. 3C. The P− typesilicon film is deposited to a thickness desired for the channelthickness of the device. The P− type polysilicon film is thenanisotropically etched so that P− type silicon film 302 is removed fromhorizontal surfaces and remains on vertical surfaces such as thesidewalls of pillar 306. In this way the P− type silicon film is formedadjacent to the pillar and bridges the source/drain regions across theinsulator 304. The charge storage medium 211 and control gate 218 canthen subsequently be formed as in the other pillar devices.

FIG. 4 shows another embodiment of the three terminal stackablenonvolatile pillar memory device of the present invention. FIG. 4 is athree terminal stackable non-volatile pillar memory device whereSchottky contacts form the source and drain regions of the device. TheSchottky contact MOSFET 400 of the present invention includes a firstmetal contact 402 formed on a first input/output 204. A doped siliconbody or channel 404 such as N type silicon doped to a concentrationlevel between 1×10¹⁶ to 1×10¹⁸ atoms/cm³ and having a thickness desiredfor the channel length is formed on metal contact 402. A second metalcontact 406 is formed on and in direct contact with silicon body 404. Asecond I/O is then formed on second metal contact 406. First metalcontact 402 and second metal contact 406 are formed of a material suchas platinum silicide, tungsten silicide and titanium silicide and to athickness that forms a Schottky barrier contact with silicon body 404.The first metal contact 402, silicon body 404, and second metal contact406 are each directly vertically aligned to one another to form a pillar408 as shown in FIG. 4. Memory device 400 also includes a charge storagemedium 211 directly adjacent to and in contact with silicon body 404 asshown in FIG. 4. Additionally, memory device 400 includes a control gateadjacent to and in direct contact with the charge storage medium 211.When a channel is formed in silicon body 404, current (e.g., readcurrent I_(R)) flows from metal contact 402 to metal contact 406 in adirection perpendicular (z) to the surface of the substrate (x-y) onwhich memory device 400 is formed.

FIG. 5 illustrates another embodiment of a three terminal nonvolatilememory device in accordance with the embodiment of the presentinvention. FIG. 5 illustrates a gated diode memory device 500. Memorydevice 500 includes a P+ type silicon film contact region 502 having adopant density between 1×10¹⁹ to 1×10²¹, preferably 1×10¹⁹ to 1×10²⁰atoms/cm³ and a thickness between 500-1000 Å. A P− silicon film 504having a doping density between 1×10¹⁶ to 1×10¹⁸ atoms/cm³ is formed onand in direct contact with P+ silicon film 502. An N+ type siliconcontact region 506 having a doping density between 1×10¹⁹ to 1×10²¹,preferably 1×10¹⁹ to 1×10²⁰, atoms/cm³ and a thickness between 500-1000Å is formed directly on P− silicon film 504. In an embodiment of thepresent invention P+ silicon film 502, P− silicon film 504, and N+silicon film 506 are each vertically aligned with one another to form apillar 508 as shown in FIG. 5. Memory device 500 also includes a memorystorage medium 211 formed adjacent to and in direct contact with P−silicon film 504 and N+ silicon film 506 as shown in FIG. 5. Adjacent toand in direct contact with charge storage medium 211 is a control gate218. Additionally, like transistors 100, 200, 300, and 400, when gateddiode 500 is turned “on” a current (I) travels from P+ silicon film 502to N-type silicon film 506 in a direction perpendicular (z) to the plane(x-y) of the substrate 501 on or above which device 500 is formed.

Although devices 200-500 have been shown with a charge storage mediumcomprising a continuous film floating gate 214 isolated by a tunneldielectric 212 and a control gate dielectric 216, the floating gate neednot necessarily be formed from a continuous conductive film of siliconor metal but can alternatively be formed from a plurality of aelectrically isolated nanocrystals 602 as shown in FIG. 6. Nanocrystalsare small clusters or crystals of a conductive material that areelectrically isolated from one another. An advantage of the use ofnanocrystals for the floating gate is that because they do not form acontinuous film, nanocrystal floating gates are self isolating.Nanocrystals 602 enable multiple self-isolating floating gates to beformed around a single silicon body 206. For example, with a square orrectangular shaped pillar, a floating gate can be formed on each side ofthe silicon body or channel enabling four or more isolated floatinggates to be formed around a single square pillar. In this way, multiplebits can be stored in each pillar memory. Similarly, becausenanocrystals form a non-continuous film, floating gates can be formedafter two or more levels of pillars are formed without worrying aboutshorting of the floating gate of one cell level to the floating gates toadjacent cells lying directly above or below (i.e., verticallyadjacent). Yet another advantage of the use of nanocrystals for floatinggates is that they experience less charge leakage than do continuousfilm floating gates.

Nanocrystals 602 can be formed from conductive material such as silicon,tungsten, or aluminum. In order to be self isolating, the nanocrystalsmust have a material cluster size less than one-half the pitch of thecell so that floating gates from vertically and horizontally adjacentcells are isolated. That is, the nanocrystals or material clusters 602must be small enough so that a single nanocrystal 602 cannot bridgevertically or horizontally adjacent cells. Silicon nanocrystals can beformed from silicon by utilizing chemical vapor deposition to decomposea silicon source gas such as silane at very low pressure. Similarly, atungsten nanocrystal floating gate can be formed by chemical vapordeposition by decomposing a tungsten source gas such as WF6 at very lowpressures. Still further, an aluminum nanocrystal floating gate can beformed by sputter deposition at or near the melting temperature ofaluminum.

Additionally, alternative to the use of a dielectric isolated floatinggate to store charge in the memory devices of the present invention, onecan use a trapping layer formed in the dielectric stack 702 as shown inFIG. 7. For example, the charge storage medium can be a dielectric stack702 comprising a first oxide layer 704 adjacent to the silicon body orchannel, a nitride layer 706 adjacent to the first oxide layer and asecond oxide layer 708 adjacent to the nitride layer and adjacent to thecontrol gate 218. Such a dielectric stack 702 is sometimes referred toas an ONO stack (i.e., oxide-nitride-oxide) stack. Other suitable chargetrapping dielectric films such as an H+ containing oxide film can beused if desired.

It is to be appreciated that each of the memory devices 200-500 shown inFIGS. 2-5 can be made of opposite polarity by simply reversing theconductivity type of each of the silicon regions in the pillar andmaintaining concentration ranges. In this way, not only can NMOS devicesbe fabricated as shown in FIGS. 2-5, but also PMOS devices can be formedif desired. Additionally, the silicon films used to form the pillars ofthe device may be single crystal silicon or polycrystalline silicon.Additionally, the silicon film can be a silicon alloy film such as asilicon germanium film doped with N type or P type conductivity ions tothe desired concentration.

Additionally, as shown in FIGS. 1-3 and 5, the pillars 108, 208, 308,and 508 are fabricated so that the contacts and body are aligned withone another when viewed from the top. This may be achieved by firstforming an I/O 204 and then blanket depositing the pillar film stack(e.g., N+/P−/N+) as shown in FIG. 8A. The film stack 802 can then bemasked and all three films anisotropically etched in a single step asshown in FIG. 8B to form a pillar 804. An explicit pillar formation stepcan form a pillar having any desired shape. For example, the pillar 804can take the shape of a square as shown in FIG. 8B or can take the shapeof rectangle, or a circle when viewed from above.

Alternatively, as shown in FIGS. 9A and 9B, a pillar can be formed bythe intersection of the patterning of the first and second I/O's. Forexample, a pillar can be formed by first blanket depositing a first I/Oconductor 900 followed by the sequential blanket deposition of the filmstack 902 (e.g., N+/P−/N+) of the desired pillar. The first I/O film 900and the pillar film stack 902 are then etched to form a plurality ofpillar strips 904 as shown in FIG. 9 a. During subsequent processing topattern the second I/O, the second I/O 906 is etched in a directionperpendicular or orthogonal to the plurality of strips 904. The etchstep used to pattern the second I/O 906 is continued so as to etch awaythe pillar film stack 902 from the portions of the strip 904 which arenot covered or masked by the second I/O 906. In this way, a pillar 908is formed at the intersection of the first and second I/O's. The pillar908 is formed in direct alignment with the intersection or overlap ofthe first and second I/O's. The intersection technique of forming apillar is advantageous because it saves additional lithography steps.

The charge storage medium of the memory device of the present inventioncan be formed utilizing a “spacer etch” technique. For example, as shownin FIG. 10A-10E a pillar 1000 or a pillar strip is first formed. A firsttunnel dielectric 1002 is then blanket deposited over the pillar 1000.Next, a floating gate material 1004 is blanket deposited over the tunneldielectric 1002. The floating gate dielectric material is deposited to athickness desired for the floating gate. The floating gate material canbe nanocrystals or can be a continuous conductive film. The floatinggate material 1004 and the tunnel dielectric 1002 are thenanisotropically etched back to remove them from horizontal surfaces suchas the top of pillar 1000 and between adjacent pillars so as to leave afloating gate 1008 isolated by a tunnel dielectric on the sidewalls ofthe pillar 1000 or strip. If the floating gate is made from a continuousconductive film, as opposed to nanocrystals, then care must be taken toensure the complete removal of the floating gate material 1004 frombetween adjacent cells so that the floating gates 1008 of adjacent cellsare isolated.

It is to be appreciated that when the floating gate is made ofnanocrytals or when the charge storage medium is a trapping dielectric,the films need not necessarily be etched from horizontal surfacesbetween adjacent cells because these films do not electrically coupleadjacent cells. If desired, however, charge trapping dielectric andnanocrystal floating gates can be anisotropically etched back. Next, asshown in FIG. 10D, a control gate dielectric 1006 is blanket depositedover floating gate 1008 and the top of pillar 1000.

A control gate can also be formed using a “spacer etch” technique. Insuch a case, a control gate material 1010, such as doped polysilicon, isblanket deposited over the control gate dielectric 1006 to the thicknessdesired of the control gate as shown in FIG. 10D. The control gatematerial 1010 is then anisotropically etched back as shown in FIG. 10Eto remove the control gate material 1010 from horizontal surfaces suchas on top of control gate dielectric 1006 and between adjacent pillarsor strips and form a control gate 1012 adjacent to control gatedielectric 1006. The control gate dielectric 1006 protects theunderlying silicon pillar 1000 from being etched during the anisotropicetch of the control gate material.

While it is necessary to isolate the floating gate from adjacent cells,the control gate can be shared between horizontal or vertically adjacentcells. Horizontally shared control gates can be achieved by utilizinglithography to form a conductor strip which connects horizontallyadjacent transistors. Alternatively, as shown in FIGS. 11A-11C,horizontal coupling of adjacent cells can be achieved by accuratelycontrolling the space between adjacent cells 1100 so that a minimalspace 1102 is placed between cells having control gates to be coupledtogether while larger gaps 1104 are placed between cells having controlsgates which are to be isolated as shown in FIG. 11A. In this way, when acontrol gate material 1106 is deposited, it completely fills the minimumor small gaps 1102 between adjacent cells while leaving only a thin filmon the large gaps 1104 between cells to be isolated as shown in FIG.11B. During the anisotropic etch, the thin control gate material in thelarge gaps is completely removed, isolating adjacent control gates,while a portion 1108 of the thicker control gate material 1106 in thesmall gap remains, so that it bridges adjacent cells and coupleshorizontally adjacent cells as shown in FIG. 11C.

Additionally, vertical sharing of the control gate can be achieved byforming a control gate plug between adjacent cells after two or morelevels of pillar have been formed as shown in FIG. 12A and 12B. Acontrol gate plug can be formed by blanket depositing a conductive filmsuch as a doped polysilicon film or a tungsten film 1200 over andbetween two or more levels of pillars and then planarizing or patterningthe portion of the tungsten film above the pillars to form a plugbetween pillars. In this way, the control gate would be shared withdevices on two or more vertical levels and between horizontally adjacentcells.

A method of integrating the pillar memory device of the presentinvention into a multi-level array of storage cells will now bedescribed. As shown in FIG. 13, the fabrication starts by providing asubstrate 1300 on which the multilevel array of storage devices is to beformed. Substrate 1300 will typically include a lightly dopedmonocrystalline silicon substrate 1302 in which transistors such asmetal oxide semiconductor (MOS) transistors are formed. Thesetransistors can be used as, for example, access transistors or they canbe coupled together into circuits to form, for example, charge pumps orsense amps for the fabricated memory devices. Substrate 1300 willtypically also include multiple levels of interconnects and interlayerdielectrics 1304 used to couple transistors in substrate 1302 togetherinto functional circuits. The top surface 1306 of substrate 1300 willtypically include an insulating layer or passivation layer to protectthe underlying transistors and interconnects from contamination. The topsurface 1306 will typically contain electrical contact pads to whichmultilevel arrays of memory devices of the present invention can beelectrically coupled in order to make electrical contact with thetransistors in silicon substrate 1302. In an embodiment of the presentinvention, the memory devices are physically isolated and separated fromthe single crystalline substrate by multiple levels of interconnects anddielectric 1304. The top surface of passivation or insulating layer 1306will typically be planarized to enable uniform and reliable fabricationof multiple levels of the charge storage devices of the presentinvention. FIG. 13A shows a cross-sectional view through the substratewhile FIG. 13B illustrates an overhead view of the substrate lookingdown at the plane of the substrate 1300 across which the devices of thepresent invention are fabricated. According to one embodiment of thepresent invention, the memory devices are physically separated frommonocrystalline silicon substrate 1302. In an alternative embodiment ofthe present invention, memory devices can be fabricated on a glasssubstrate 1300 such as used in flat panel displays.

A process of forming a multilevel array of memory devices in accordancewith an embodiment of the present invention begins by blanket depositinga first conductor layer 1308 over surface 1306 of substrate 1300.Conductor 1308 can be any suitable conductor such as but not limited to,titanium silicide, doped polysilicon, or a metal such as aluminum ortungsten and their alloys formed by any suitable technique. Conductorlayer 1308 is to be used as, for example, a bitline or a wordline tocouple a row or column of memory devices together. Next, a stack 13 10of films from which the first level of pillars is to be fabricated isblanket deposited over conductor 1308 as shown in FIG. 13A. For example,in one embodiment the pillar is to comprise an N+ source/drain region, aP− silicon body, and an N+ silicon source/drain region. A suitable filmstack 1310 can be formed by first blanket depositing an amorphoussilicon film by chemical vapor deposition (CVD) which is in situ dopedwith N type impurities to a doping density between 1×10¹⁹ to 1×10²¹,preferably 1×^(19 to) 1×10²⁰, atoms/cm³. Next, a P− silicon film isdeposited over the N+ silicon film 1312, by for example, depositing anamorphous silicon film by chemical vapor deposition and which is in situdoped with P type impurities (e.g., boron) to a dopant density ofbetween 1×10¹⁶ to 1×10¹⁸ atoms/cm³. An N+ silicon film 1316 is thenblanket deposited over P− silicon body 1314 by depositing a amorphoussilicon film by chemical vapor deposition and in situ doping it to alevel between 1×10¹⁹ to 1×10²¹, preferably 1×10¹⁹ to 1×10²⁰, atoms/cm³.The amorphous silicon films can then be converted into polycrystallinesilicon through a subsequent anneal. Alternative to in situ doping, thestack of films can be deposited as undoped silicon and then implanted ordiffused with dopants.

It is to be appreciated that other memory devices in accordance with thepresent invention can be fabricated by depositing appropriate filmstacks to achieve their pillar configurations such asmetal/silicon/metal strip to form a device 400 as shown in FIG. 4, aP+/P−/N+ stack to form a device 500 as shown in FIG. 5, as well as anN+/SiO₂/N+ stack to form a device 300 as shown in FIG. 3A. Next, asshown in FIGS. 14A and 14B the blanket deposited film stack 1310 andmetal conductor 1308 are patterned utilizing well-known photolithographyand etching techniques to form a plurality of pillar strips 1318. Thefilms of the deposited film stack 1310 and metal conductor 1308 areetched in alignment with one another and form strips with verticalsidewalls.

Next, as shown in FIG. 15A and 15B, if desired, the substrate can besubjected to threshold adjusting ion implantation steps in order toalter the doping density of the surface or face of the P type siliconregion on each strip. That is, at this time, a first ion implantationstep 1315 can be used to implant one surface of pillar 1318 with P typedopants to increase its P type doping density or can be implanted with Ntype dopants to counterdope and decrease its P type doping density.Similarly, after the first implant 1315, the substrate can be rotatedand subjected to a second ion implantation step 1317 to alter the dopingdensity of the opposite side or face of pillars strips 1318. Thethreshold adjustment implants should be of a sufficient dose tosufficiently alter the threshold voltage of each face so as to be ableto sufficiently distinguish or sense different read currents associatedwith each face. The angle of the ion implantation step is chosen so thatthe bulk of the implantation occurs into the surface of the P type body1314. The angle of the implant is dependent upon the strip height aswell as on the spacing between strips 1314.

Next, as shown in FIG. 16A and 16B, tunnel dielectric 1320 is formedover the sidewalls and the top of strip 1318 as well as on substrate1300 between strips 1318. Tunnel dielectric can be an oxide, a nitride,a oxynitride, or other suitable dielectric. The tunnel dielectric 1320is preferably deposited utilizing a plasma deposition or growth processat a temperature of less than 750° C. and preferably less than 600° C.The tunnel dielectric 1320 is formed to a thickness and quality toprevent breakdown and leakage at operating conditions. Next, as alsoshown in FIGS. 16A and 16B, a floating gate material 1322 is blanketdeposited over tunnel dielectric 1320. In a preferred embodiment of thepresent invention, the floating gate material is formed of nanocrystals.

Silicon nanocrystals can be formed by depositing silicon in a mannerwhereby silicon has a very high surface diffusivity relative to itssticking coefficient. For example, silicon nanocrystals can be formed bychemical vapor deposition (CVD), by decomposing silane (SiH₄) at a verylow pressure, between 1 millitorr to 200 millitorr, at a temperaturebetween 250-650° C. In such a process, a very thin deposition, between50-250 Å, will form little islands 1322 of silicon. If H₂ is includedwith silane during the deposition, higher pressures can be utilized andstill obtain nanocrystals. In an alternative embodiment of the presentinvention, metal nanocrystals such as aluminum nanocrystals, can beformed by sputtering from a metal target at a temperature near themelting temperature of the metal, so that the metal agglomerates andforms nanocrystals. Tungsten nanocrystals can be formed by chemicalvapor deposition utilizing a reactant gas mix comprising a tungstensource gas such as WF₆ and germane (GeH₄). In still yet anotherembodiment of the present invention, a continuous film of floating gatematerial can be deposited and then caused to precipitate (by heating) tocause islands to form in the film.

It is to be appreciated that although nanocrystals are preferred for thefloating gate because of their self isolating quality, the floating gatecan be formed from a continuous film such as, but not limited to, ametal such as tungsten or a silicon film such as polycrystalline oramorphous silicon doped to the desired conductivity type (typically N+silicon for an N+/P−/N+pillar). If a continuous film is used as floatinggate material 1322, the film 1322 would be anisotropically etched atthis time to remove the portion of the floating gate material 1322between strips 1318 to electrically isolate the strips.

Next, as also shown in FIGS. 16A and 16B, a control gate dielectric 1324is blanket deposited over and onto floating gate material ornanocrystals 1322. The control gate dielectric 1324 is a depositeddielectric of, for example, an oxide or oxynitride film formed by aplasma enhanced deposition process to reduce the deposition temperature.The control gate dielectric 1324 has a thickness similar to the tunneldielectric 1320 but slightly, e.g., 20-30 Å, thicker. The control gatedielectric 1324 is used to isolate the floating gate from a subsequentlyformed control gate. The thickness and quality of the control gatedielectric depends upon the program threshold voltage for programmingand unprogramming the memory cell. As discussed above, the thickness ofthe tunnel dielectric as well as the thickness of the P type siliconbody or channel are dependent upon the programming voltage desired.

Next, as shown in FIGS. 17A and 17B, a control gate material 1328 isblanket deposited on and over strips 1318. The control gate material isformed to a thickness at least sufficient to fill the gaps betweenadjacent strips. Typically, a conformal film deposited to a thickness ofat least one-half the width of the gap 1330 will ensure complete fillingof gap 1330. In an embodiment of the present invention, the control gatematerial 1328 is a doped polycrystalline silicon film formed by chemicalvapor deposition. Alternatively, the control gate can be formed fromother conductors such as a blanket deposited tungsten film formed bychemical vapor deposition utilizing WF₆. Next, as shown in FIGS. 18A and18B, the control gate film 1328 is planarized back by for example,chemical mechanical polishing until the top surface of the control gateis substantially planar with the control gate dielectric on the top ofstrips 1318. A plasma etch process is then utilized to recess 1331 thetop surface of the control gate material below the top surface of strips1318 and preferably to slightly above the top source/body junction(e.g., junction of N+ silicon film 1316 and P− silicon film 1314) asshown in FIG. 18A. The control gate dielectric 1324 on the top of strips1318 protects strips 1318 from etching during the recess etch. After therecess etch, control gates 1332A and B have been formed.

Next, an interlayer dielectric (WLD) 1334 such as an oxide, is blanketdeposited over the top of strips 1318 as well as on and into recesses1331 over control gate 1332. The deposited oxide layer 1334, as well asthe control gate dielectric, the nanocrystals, and tunnel dielectric onthe top of strips 1318 are then polished or etched back as shown inFIGS. 19A and 19B to reveal and open the surface of the top source/drainregion (e.g., N+ film 1316) of each pillar strip 1318.

Next, as shown in FIGS. 20A and 20B, a second conductor layer 1336 isblanket deposited over and in contact with the top source/drain region(N+ source/drain region 1316) as well as over and onto ILD 1334. Thesecond conductive layer 1336 will be used to form a second input/output(e.g., a bitline or a wordline) for the first level of memory devicesand will be used to form a first input/output (e.g., a wordline or abitline) for the second level of memory devices. Second conductive layer1336 can be formed of materials and to thicknesses similar to firstconductive layer 1308.

Next, a film stack 1338, such as an N+/P−/N+ stack, used to form thesecond level of pillars, is blanket deposited over second conductivelayer 1336 as shown in FIGS. 20A and 20B. The film stack 1338 can beformed with the same materials and to the same thickness as used forfilm stack 1310. Alternatively, if a different type of memory device isdesired, then a film stack corresponding to that device type would beformed.

Next, as illustrated in FIG. 21A and 21B, the second pillar stack 1338and the second conductive layer 1336 are patterned with well-knownphotolithography and etching techniques to form a plurality of secondpillar strips 1340 orthogonal or perpendicular to the first plurality ofpillar strips 1318. It is to be appreciated that the films of the secondpillar stack 1338 and the second conductive layer 1336 are etched inalignment with one another to form a strip with substantially verticalsidewalls.

FIGS. 22A and 22B show the substrate of FIGS. 21A and 21B rotated 90°.

Once the second pillar film stack 1338 and second conductor 1336 havebeen patterned by etching into a strip 1340, the etch is continued toremove the portion 1341 of the first pillar strips 1318 not covered ormasked by the second pillar strips 1340 as shown in FIGS. 23A and 23B.The etch is continued until the first conductive layer 1308 is reached.In this way, as shown in FIGS. 23A and 23B, a first level of square orrectangular pillars 1342 have been formed from first pillar strips 1318at the intersections or overlaps of the first and second I/O 1308 and1336 (shown as M1 and M2 in FIG. 23A). In an embodiment of the presentinvention square pillars having a width of less than 0.18 μm are formed.It is to be appreciated that the etch step preferably uses an etch thatcan selectively etch the pillar strip with respect to the ILD 1334 andthe tunnel and control gate dielectrics. For example, if the pillarcomprises doped silicon and the ILD and the tunnel and control gatedielectrics are oxides, then a plasma etch utilizing Cl₂ and HBr canetch silicon without significantly etching the oxide ILD or tunnel andcontrol gate dielectrics. It is to be appreciated that ILD 1334 protectsthe underlying silicon control gate 1332 from being etched as shown inFIG. 23C. Additionally, the purpose of ILD 1334 is to electricallyisolate control gates 1332 from subsequently formed control gates forthe second level of pillars.

At this time, if desired, the substrate can be subjected to successiveion implantation steps to alter the doping density of each newlyrevealed surface of P type body 1314 of pillar 1342 (see FIG. 23A) inorder to alter the doping density of each face and therefore thethreshold voltage of each face.

Next, as shown in FIG. 24, a tunnel dielectric 1344, a nanocrystalfloating gate material 1346, and a control gate dielectric 1348 are eachsuccessively blanket deposited over substrate 1300 to form a tunneldielectric/floating gate/control gate on the sidewalls of pillar devices1342 as well as along the sidewalls of the second pillar strip 1340 (seeFIG. 23A). This film stack also forms along the top surface of thesecond pillar strips 1340 as well as on the first conductor 1308 betweenthe first level of pillars 1342 and on ILD 1334.

The floating gate material need not be anisotropically etched to removefloating gate material from gaps 1343 between adjacent pillars 1342 inorder to isolate the pillars because although the floating gate materialis conductive the non-continuous nature of the nanocrystals providesisolation between the pillars. In this way, the tunnel dielectric,floating gate, and control gate dielectric can be used to isolate asubsequently formed control gate from the first metal conductor.Additionally, because the floating gate 1346 is formed fromnanocrystals, it is self isolating from the floating gate positioneddirectly above in Level 2 even though they have been formed at the sametime.

Next, as shown in FIG. 25A a control gate 1350 is formed between secondpillar strip 1340 as well as in the gaps 1343 between pillars 1342. Thecontrol gate can be formed as discussed above with respect to FIGS.17-20 whereby a control gate film, such as doped polysilicon, is blanketdeposited to fill the gaps 1343 between adjacent pillars 1342 as well asthe gaps between second pillar strips 1340. Optionally, the control gatefilm would then be polished and recessed back below the top surface ofthe N+ source/drain regions and a second ILD 1352 formed in the recessesas shown in FIG. 25A to allow additional layers to be added. ILD 1352,the tunnel dielectric/floating gate/control gate dielectric on the topof the second pillar strip 1340 would then be polished back to revealthe top N+ source/drain regions of strips 1340.

At this point, the fabrication of the first level of memory devices iscomplete.

Each pillar 1342 on the first level includes a separate floating gateand control gate on each face of the pillar for a total of fourindependently controllable charge storage regions as shown in FIG. 26.That is, as illustrated in FIG. 26, pillar 1342 contains a first pair ofcontrol gates 1332A and B formed along laterally opposite sidewalls ofthe pillar 1342. The control gates 1332A and B are each also shared withthe horizontally adjacent pillars. Pillar 1342 also contains a secondpair of control gates 1350A and B formed along laterally opposite thirdand fourth faces of pillar 1342. Each control gate 1350 will be sharedwith the subsequently formed pillar memory device position verticallyabove, in Level 2, as well as with horizontally adjacent pillars 1342 inthe same level. Because pillar 1342 contains four independentlycontrollable control gate and four associated and isolated floatinggates, each pillar memory device 1342 is able to store multiple states.

The process as described with respect to FIGS. 20-25 can be repeatedagain to complete the fabrication of memory devices on the second leveland to begin the fabrication of the memory device on the third level.That is, as shown in FIGS. 27A and 27B (FIG. 26 rotated 90°) the stepsof FIGS. 20-25 can be repeated to form third pillar strips 1360orthogonal to the second pillar strips 1340 which are used to patternthe second pillar strips 1340 into a plurality of second pillars 1362 ona second level and to form a second pair of control gates 1364 adjacentto the second pillars.

In this way, a second level of memory pillars 1362 are fabricated whichcontain four independently controllable control gates and fourassociated and isolated floating gates. A first pair of control gates1350A and B are formed along laterally opposite sidewalls of the secondlevel of pillars 1362 and are shared with memory pillar 1342 located onthe first level as well as with horizontally adjacent cells. A secondpair of control gates 1364A and B are formed along the third and fourthlaterally opposite faces of the second level of pillars 1362 and areshared with the subsequently formed pillars in the third level of thememory array.

The above described processes can be repeated as many times as desiredto add additional levels of pillar memory to the array. The final levelof memory cells can be patterned from a pillar stack strip whilepatterning the final I/O.

Although the three terminal memory pillar devices of the presentinvention have been shown integrated into a three dimensional memoryarray in a specific preferred embodiment, it is to be appreciated thatother methods may be utilized to fabricate a three dimensional memoryarray without departing from the scope of the present invention.

2. Memory Cells Utilizing a Charge Storage Medium Located Above or Belowa Semiconductor Region

In FIG. 29A, the cell comprises a diode and a stack comprising regions2921, 2922 and 2923. The region 2921 comprises a first dielectric regionand the region 2923 comprises a second dielectric region. Disposedbetween these regions is a storage region 2922 which is used to trapcharge. It is primarily this region that retains charge and thusprovides the “memory” of the cell. As will be described below, chargecan be electrically placed within the region 2922, electrically sensedand electrically removed from the region 2922.

The region 2921 comprises an oxide with a thickness, typically between1-5 nm, and preferably 2-3 nm. In one embodiment, the region 2921 isreferred to in this application as a tunnel dielectric. The region 2922is a region that stores trapped charge, as known in the prior art suchas a nitride region (discussed in more detail below). In one embodiment,the region 2922 is referred to in this application as a storagedielectric. The region 2923, which may comprise an oxide, acts as abarrier for retaining a trapped charge and in one embodiment is referredto in this application as a blocking dielectric. It may have thicknessessimilar to those of region 2921.

Because electrons carry the forward current in the diode once punchthrough occurs, these are the species that are trapped at the tunneldielectric-storage dielectric interface 2925 and within the region 2922.Note that these electrons are of a polarity to encourage the prematureinversion of the N region at the interface region 2921. Thus, storedelectrons reduce the voltage at which first appears thenegative-resistance portion of the cell's characteristic, see curve 2926versus curve 2927 of FIG. 29B.

In one embodiment, programming consists of applying a sufficient forwardbias to the diode to cause the device to conduct and allowing forwardcurrent to persist long enough for sufficient charge to become trappedthereby shifting the voltage threshold from the peak forward voltageshown for curve 2927 to the peak forward voltage shown for curve 2926.While throughout the discussion that follows, binary programming isdiscussed, multiple bits may be stored per cell by employing multiplevalues of threshold shifts. By analogy, some flash memories store 2-4bits per cell or even more.

Reading (sensing) may be performed by applying a forward voltage thatfalls between the peaks 2928 and 2929. If current in excess of apredetermined threshold value flows, the cell is programmed; ifconduction does not occur it is not programmed. The conduction that doesflow through a programmed cell during a read operation reinforces thetrapped charge.

Erasing is accomplished by applying a sufficient reverse bias to thememory cell that electrons tunnel out of the traps, through the blockingoxide 2923 or through the flow of holes so as to neutralize the trappedelectrons. This action necessarily requires the diode to operate inbreakdown, so the erase voltage will require at least the lower end of abreakdown voltage.

A. Two Terminal Cell in a Substrate

Referring to FIG. 30, a first embodiment of the invented memory cell isillustrated disposed in a p-type substrate 2930. A diode (steeringelement of the cell) is formed in the substrate comprising an n− region2932, doped, for instance to a level of 5×10¹⁶-10¹⁸ cm⁻³, and a p+region 2931, doped to >10¹⁹ cm⁻³ formed within the n− region 2932. Theseregions may be formed with well-known methods such as diffusion or ionimplantation.

A storage stack comprising a dielectric (e.g., oxide) region 2933,trapping layer 2934 and a second dielectric (e.g., oxide) region 2935 isformed on the region 2932.

The dielectric region 2933 may be a grown oxide layer or a depositedsilicon dioxide region. When comprising oxide, this region may be 1-5 nmthick. Ordinary processing may be used to form these regions.

The trapping region 2934 and the other trapping regions discussed inthis application may be formed from a compound of nitrogen as well asother materials. In the prior art, silicon nitride (nitride) was mostcommonly used for this purpose. Other layers that may be used that havecompounds of nitrogen are oxynitride (ON) and oxide-nitride-oxide (ONO).Other materials, alone or in combination, that exhibit charge trappingcharacteristics can be used. For instance, alumina (Al₂O₃) and silicondioxide with insulated regions of polysilicon exhibit thesecharacteristics. The trapping region is generally between 2-20 nm thick,and preferably 3-10 nm thick.

The regions 2933 and 2934 have thicknesses determined by factorswell-known in the art for SONOS memories. For example, the tunneldielectric region needs to be thin enough to permit tunneling withoutexcess voltage drop and to provide longevity, while the trappingdielectric region must be thick enough not to allow significantspontaneous detrapping of charge. As mentioned above, typicalthicknesses are in the range of 1-5 nm, and preferably 2-3 nm for theoxide region 2933 and 3-10 nm for the trapping region where nitride isused.

The layer 2935 is an oxide or other dielectric region which may have thesame thickness as region 2933. Other dielectrics that may be usedinclude perovskites, ceramics, diamond (and diamond-like films), siliconcarbide, and undoped silicon (including polysilicon). This region may beformed by well-known deposition techniques. The region 2933, aspreviously mentioned, is referred to as a tunnel dielectric layer and isresponsible, at least in part, for the negative-resistancecharacteristics previously discussed. The layer 2935, on the other hand,prevents trapped charge from region 2934 from leaking to, for instance,contact 2938. Hence, layer 2935 is sometimes referred to as the blockingdielectric.

The storage stack comprising regions 2933, 2934 and 2935 may befabricated in a single, continuous process where, for instance, gasmixtures in a deposition chamber are altered to first provide oxide thennitride and finally oxide again. Because of the relative thinness ofthese regions, the entire stack may be laid down in a matter of seconds.

To operate the cell of FIG. 30 first assume that upon manufacturing thetrapping layer is neutral, that is, there is no trapped charge in thetrapping region 2934. To place charge in the region 2934 the anodecontact 2937 is brought to a positive potential relative to the contact2938 in order to forward bias the diode defined by the regions 2931 and2932 until the potential reaches the voltage 2929 shown in FIG. 29B. Nowtunneling occurs through the oxide 2933 as well as the oxide 2935 andcharge is trapped within the region 2934. The amount of charge trappeddepends on total current flow and the trapping efficiency of the region2934.

To sense the presence of this charge, a potential is applied betweenlines 2937 and 2938 again to forward bias the diode defined by regions2931 and 2932. However, this time the potential is in a range greaterthan the voltage 2928 shown in FIG. 29B but less than the voltage 2929.If current in excess of a predetermined threshold flows, then it isknown that charge is trapped in the region 2934. On the other hand, ifsuch current flow does not occur, it is known that little or no chargehas been stored in the layer. In this way it can be determined whetherthe cell is programmed or not programmed for the binary data case. Aspreviously mentioned, different levels of charge may be placed in thetrapping layer 2934, and the voltage at which said current flow occurs(say between voltages 2928 and 2929) can be determined. This correspondsto the amount of charge in the layer 2934 that can be used to providemore than one bit of data from an individual cell.

It should be noted that during a read operation the read current passesthrough a programmed cell, and then passes through the region 2933,trapping region 2934 and the oxide region 2938. This is unlike thetypical sensing that occurs where trapped charge is used to shift athreshold voltage in, for example, a field-effect transistor where thecurrent does not pass through the trapped charge region itself whenreading the state of the cell. As mentioned earlier, when the currentdoes pass through the region 2934 for reading it, in effect, refreshesthe cell; that is if the cell was originally programmed it will remainprogrammed when the data is read from the cell.

Care must be taken when reading data from the cell not to exceed acurrent represented by line 2924. If a current exceeds this limit, forexample, 5000-10,000 amps/cm², one or both of the oxide regions 2933 or2935 may be permanently damaged and may likely provide a short circuitor open circuit.

To erase the data in the cell the diode is reverse biased: that is, theanode is brought negative relative to the cathode. When sufficientpotential is applied, the diode breaks down and (e.g., avalanches,Zeners, or punches through) and strips the charge from the region 2934.It may be necessary to float the substrate 2930 during erasing toprevent forward biasing the junction between layer 2932 and thesubstrate 2930. Other isolation methods such as shallow-trench isolation(STI) or silicon-on-insulator (SOI) may be used as well.

B. Three Terminal Cell in the Substrate

In FIG. 31 the cell incorporates a field-effect transistor having asource and drain region and a gate 2946. Regions 2941 and 2942 areformed in alignment with gate 2946 in the substrate 2940 as iswell-known in the art. A stack comprising an oxide region 2943, trappingregion 2944 and oxide region 2945 are formed on region 2941. The regions2943, 2944 and 2945 may be the same as regions 2933, 2934 or 2935 ofFIG. 30.

In this embodiment, rather than forward biasing a diode, a positivepotential is applied to gate 2946 and contact 2948 is maintainedpositive relative to contact 2947. This is done for programming andreading of the cell. To erase the cell, contact 2948 is negativerelative to contact 2947, causing trapped charge to be removed from theregion 2944. For both the embodiments of FIGS. 30 and 31 it may be moredesirable in some memory arrays to erase an entire array at one timethrough the substrate by reverse biasing, say, the region 2941 andsubstrate 2940. If desired, the cells of FIGS. 30 and 31 may be formedabove the substrate rather than in the substrate and/or stacked in threedimensions.

C. Three-Dimensional Embodiment Empltoying Rail-Stacks

In U.S. application Ser. No. 09/560,626, filed Apr. 28, 2000, and itsco-pending continuation-in-part, U.S. application Ser. No. 09/814,727,filed on Mar. 21, 2001 both assigned to the assignee of the presentinvention and entitled “Three-Dimensional Memory Array Method ofFabrication,” a three-dimensional memory array fabricated on thesubstrate and employing rail-stacks is disclosed. The technologydescribed in this patent application may be used to fabricatethree-dimensional charge trapping or storage memories in accordance withthe present embodiment of present invention, as discussed below.

In FIG. 32, three full levels of a memory array are shown, specificallylevels 2950, 2951 and 2952. Each level comprises a plurality ofparallel, spaced-apart rail-stacks. Rail-stacks 3 and 5 of FIG. 32extend in a first direction and rail-stacks 4 and 6 extend in a seconddirection, typically perpendicular to the first direction. Each of therail-stacks of FIG. 32 includes a conductor or input/output at thecenter of the rail stack and semiconductor regions disposed on bothsides of the conductor. For the embodiment of FIG. 32, first alternaterail-stacks, for instance rail-stacks 3 and 5, are fabricated from ntype polysilicon disposed on the conductors. The second alternaterail-stacks 4 and 6 have p-type polysilicon on the conductors.

More specifically, referring to rail stack 5, it includes the centerconductor or input/output 2953, for instance, an aluminum or silicideconductor, n+ regions 2954 and 2956 disposed on both sides of theconductor and n− regions 2955 and 2957 disposed on the regions 2954 and2956, respectively. The n+ regions may be doped to a level of >10¹⁹ cm⁻³and the n− regions to a level of 5×10¹⁶-10¹⁸ cm⁻³. Rail-stacks 4 and 6again include a conductor or input/output, such as conductor 2960 withp+ regions disposed on both sides of the conductor shown as p+ regions2961 and 2962 for one of the rail-stacks. The fabrication of theseregions and the entire set of rail-stacks is described in theabove-referenced application, which is hereby incorporated by referenceherein.

In the above-referenced application, a blanket layer of an anti-fusematerial is used between the rail-stacks. With the present inventionthree blanket layers are used between each level of rail-stacks.Specifically, layers 2963 are disposed between the rail-stacks 5 and 6and layers 2964 between the rail-stacks 4 and 5. The layers 2963 and2964 correspond to the layers 2933, 2934 and 2935 of, for example, FIG.30. Thus, layer 2964 comprises a dielectric (e.g., oxide) layer 2966which may have a thickness of 1-5 nm, and preferably 2-3 nm, a trappinglayer 2967 such as a silicon nitride layer which may have a thickness of2-20 nm, and preferably 3-10 nm, and a dielectric (e.g., oxide) layer2968 which may have a thickness similar to that of layer 2966. Thematerials described above for forming the regions 2933, 2934 and 2935 ofFIG. 30 apply to the layers 2966, 2967 and 2968 of FIG. 32.

A cell in the array of FIG. 32 occurs at the intersection of therail-stacks. For the embodiment of FIG. 32, the storage stack isdisposed between the p and n regions of a diode. That is, the storagestack is embedded in the steering element. For example, conductor 2960provides access to one of the cells through the p region 2961. Thelayers 2963 are disposed between the p region 2961 and n− region 2955.The other contact for this two terminal cell is through region 2954 ontoconductor 2953.

The cells of FIG. 32 are programmed, read and erased in the same manneras described above for the cell of FIG. 30.

With the configuration of FIG. 32 the diodes in adjacent pairs of memoryarray levels “point” to a common conductor. More specifically, referringto FIG. 32, the illustrated cells at memory array level 2950 have theircathodes connected to conductor 2953. The illustrated cells in memorylevel 2951 also have their cathodes connected to conductors 2953. Thissimplifies fabrication, programming, reading and erasing since theconductor 2953 serves two sets of cells.

In the above-referenced application there are several embodiments havingdifferent rail-stack configurations that may be used to fabricate athree-dimensional array using a preferred storage stack of the presentinvention.

D. Three-Dimensional Embodiment Employing Pillar Diode Structures

In U.S. Pat. No. 6,034,882 a three-dimensional memory array is disclosedemploying a plurality of levels, each level having parallel,spaced-apart conductors. The conductors at the alternate levels areperpendicular to one another. Pillar structures are formed at theintersection of a conductor in adjacent levels. The structures, asdescribed in the patent, are formed in alignment with the conductors.The fabrication technology described in this patent may be used tofabricate memory arrays employing the cell having a charge storage ortrapping region of the present embodiment.

Referring to FIG. 33 a single level of the three-dimensional memory isillustrated having a conductor or input/output 2981 at one level and aconductor 2980 at the next level in the array. A pillar structure isformed in alignment with the conductors 2980 and 2981. This pillarstructure forms a cell in accordance with the present invention.Specifically, referring to FIG. 33, the cell includes a steering elementcomprising a junction diode comprising the p+ region 2982, n− region2983 and the storage stack. As shown in FIG. 33 the storage stackcomprises a tunnel oxide region 2984, a trapping region 2986 and ablocking oxide 2985.

As described in the above patent, the conductors 2980 and 2981 areshared with cells disposed above and below the single cell shown in FIG.33.

FIG. 34 shows another embodiment where again there are spaced-apart,parallel conductors or input/output at one level such as conductor 2991and parallel, spaced-apart conductors at the next level such asconductor 2990. A pillar structure is again fabricated between theconductors 2990 and 2991 as taught by the above-referenced patent. Thedifference, however, between the structure of FIGS. 33 and 34 is thatthe storage stack comprising the blocking oxide 2993, trapping region2994 and tunnel oxide 2995 is disposed between the p and n regions ofthe diode. Specifically, the p+ region 2992 of the diode is in contactwith the blocking oxide 2993 and the n− region 2996 is in contact withthe tunnel oxide 2995.

The thicknesses of the various regions shown in FIGS. 33 and 34 and thedoping for the polysilicon diode may be similar to embodimentspreviously discussed in this application. The programming, reading anderasing of the structures of FIGS. 33 and 34 are also performed asdescribed above for the other embodiments. For the embodiments of FIGS.32, 33 and 34 the array of cells is disposed above a substrate with theperipheral circuits being formed in the substrate.

II. Self-Aligned EEPROM TFT Array

Another cell configuration that differs from pillar configuration is theself aligned TFT. The present inventors have realized that memory andlogic cell area is enlarged by misalignment tolerances that are put intoplace to guarantee complete overlap between features on differentlayers. Thus, the present inventors have developed a fully alignedmemory or logic cell structure which does not require misalignmenttolerances. Therefore, such a cell structure has a smaller area per bit(i.e., per cell) and uses fewer mask steps. The fully aligned cellstructure increases array density and decreases die size and cost.Furthermore, by optionally stacking the cells vertically in theZ-direction, the array density is further increased, which leads tofurther decreases in the die size and cost.

As described with respect to the preferred embodiments of the presentinvention, there are several different ways of achieving a fully alignedor self-aligned memory or logic cell. In cases of memory or logic cellscontaining an EEPROM, full alignment may be achieved by self alignmentof the word line to the control gate. Preferably, the word line extendssubstantially parallel to the source-channel-drain direction of theEEPROM, while the bit line extends substantially perpendicular to thesource-channel-drain direction of the EEPROM. In this configuration, bitline contact pads (i.e., source and drain electrodes) and bit linecontact vias are not required because the bit lines may be formed inself alignment with the EEPROM gate(s) directly on the source and/ordrain regions of the EEPROMs. Furthermore, since the EEPROMs are fullyself aligned, the bit and word lines may have a substantially planarupper surface, which improves the reliability of the device.

Preferably, the EEPROMs are TFTs arranged in a three dimensional virtualground array (VGA) non volatile flash memory, where each verticallyseparated level is separated from an adjacent level by an interlayerinsulating layer. However, the EEPROMs may be formed in a single levelarray or in a bulk semiconductor substrate. The preferred aspects of thepresent embodiment may also be applied to non volatile flash memoryarchitectures other than VGA, e.g., to NOR-type memory and Dual StringNOR (DuSNOR) memory. Furthermore, the present invention is not limitedto TFT EEPROM flash memory arrays, and also encompasses othersemiconductor devices within its scope. For example, the self alignedtransistors may be MOSFETs in a bulk substrate or non-EEPROM TFTs formedover an insulating substrate. These self aligned transistors may be usedas non-flash EEPROMs (i.e., EEPROMs where each transistor is erasedseparately), UV erasable PROMs (EPROMs), mask ROMs, dynamic randomaccess memories (DRAMs), liquid crystal displays (LCDs), fieldprogrammable gate arrays (FPGA) and microprocessors.

FIGS. 37-44 illustrate a method of making a TFT EEPROM nonvolatile flashmemory array 4001 according to the first preferred embodiment of thepresent invention.

First, a substrate having an insulating surface (i.e., aSilicon-On-Insulator (SOI) substrate) is provided for the formation ofthe memory array. The substrate may comprise a semiconductor (i.e.,silicon, GaAs, etc.) wafer covered with an insulating layer, such as asilicon oxide or nitride layer, a glass substrate, a plastic substrate,or a ceramic substrate. In a preferred aspect of the first embodiment,the substrate is a monocrystalline bulk silicon substrate that hasreceived prior processing steps, such as forming CMOS (complementarymetal oxide semiconductor) transistors in the substrate. The CMOStransistors may comprise peripheral or driver circuitry for the memoryarray. In the most preferred aspect, the circuitry comprises row andcolumn address decoders, column input/outputs (I/O's), and other logiccircuitry. However, if desired, the driver circuitry may be formed on aninsulating substrate, such as a silicon-on-insulator substrate, a glasssubstrate, a plastic substrate, or a ceramic substrate. Thesilicon-on-insulator substrate may be formed by any conventional method,such as wafer bonding, Separation by Implantation of Oxygen (SIMOX), andformation of an insulating layer on a silicon substrate. After theperipheral circuitry is completed, an interlayer insulating layer 4003is conformally deposited over the circuitry as shown in FIG. 37. Theinterlayer insulating layer 4003 may comprise one or more of anysuitable insulating layers, such as silicon oxide, silicon nitride,silicon oxynitride, PSG, BPSG, BSG, spin-on glass and/or a polymerdielectric layer (such as polyimide, etc.). The interlayer insulatinglayer 4003 is preferably planarized using chemical-mechanical polishing(CMP), but in other embodiments can be planarized by etch back and/orany other means.

A semiconductor active area layer 4005 is then deposited over theinsulating layer 4003 to complete the SOI substrate. The semiconductorlayer will be used for the transistor active areas. Layer 4005 may haveany desired thickness, such as 20 to 120 nm, preferably 70 nm, and ischosen so that in depletion regime the space charge region below thetransistor gate extends over the entire layer. Preferably, thesemiconductor layer 4005 comprises an amorphous or polycrystallinesilicon layer doped with first conductivity type dopants. For example,layer 4005 may be p-type doped by in-situ doping during deposition, orafter deposition by ion implantation or diffusion.

If desired, the crystallinity of the semiconductor layer 4005 may beimproved by heating the layer 4005. In other words, an amorphous siliconlayer may be recrystallized to form polysilicon or a grain size of apolysilicon layer may be increased. The heating may comprise thermal orlaser annealing the layer 4005. If desired, catalyst inducedcrystallization may be used to improve the crystallinity of layer 4005.In this process, a catalyst element such as Ni, Ge, Mo, Co, Pt, Pd, asilicide thereof, or other transition metal elements, is placed incontact with the semiconductor layer 4005. Then, the layer 4005 isthermally and/or laser annealed. During the annealing, the catalystelement either propagates through the silicon layer leaving a trail oflarge grains, or serves as a seed where silicon crystallization begins.In the latter case, the amorphous silicon layer then crystallizeslaterally from this seed by means of solid phase crystallization (SPC).

It should be noted that the deposition of amorphous or polysilicon layer4005 may be omitted if a single crystal SOI substrate is used. In thiscase, using the SIMOX method, oxygen ions are implanted deep into asingle crystal silicon substrate, forming a buried silicon oxide layertherein. A single crystal silicon layer remains above the buried siliconoxide layer.

Next, the surface of the active area layer 4005 is preferably cleanedfrom impurities and a native oxide is removed. A charge storage region4007 is then formed on the layer 4005. In the first preferred embodimentof the present invention, the charge storage region 4007 comprises anoxide-nitride-oxide (ONO) dielectric triple layer. This dielectriccomprises a first (bottom) SiO₂ layer, also called a tunnel oxide, acharge storage Si₃N_(4-x)O_(1.5x) layer, where x is 0 to 1, and a second(top) SiO₂ layer, also called a blocking oxide. The tunnel oxide iseither grown by thermal oxidation on the active area layer 4005, ordeposited over the active area layer by atmospheric pressure, lowpressure or plasma enhanced chemical vapor deposition (APCVD, LPCVD orPECVD) or other means. The tunnel oxide has a thickness of 1.5 nm to 7nm, preferably 4.5 nm. The charge storage silicon nitride or siliconoxynitride (Si₃N_(4-x)O_(1.5x)) layer is deposited over the tunneloxide, and its thickness is at least 5 nm, preferably 5-15 nm, mostpreferably 6 nm. The blocking oxide layer is arranged on the surface ofthe charge storage layer and has a thickness of 3.5 nm to 9.5 nm,preferably 5.0 nm. The charge storage and blocking layers may bedeposited by APCVD, LPCVD, PECVD, or other means, such as sputtering.

It should be noted that different materials and different layerthicknesses may be used as desired. For example, the charge storagelayer need not necessarily be formed from Si₃N_(4-x)O_(1.5x). Forexample, in an alternative aspect of the first embodiment, the chargestorage layer may be formed from a plurality of electrically isolatednanocrystals, such as silicon, tungsten or aluminum nanocrystalsdispersed in a silicon oxide, nitride or oxynitride insulating layer. Ifa nanocrystal charge storage layer is used, then the tunnel and/or theblocking oxide layers may be omitted if desired.

After the charge storage region 4007 (i.e., the ONO dielectric)formation, a first gate layer 4009 is deposited over the charge storageregion. The first gate layer 4009 may comprise any conductive layer,such as n+-doped polysilicon. Such a polysilicon layer may have anyappropriate thickness, such as 50 to 200 nm, preferably 100 nm, and anyappropriate dopant concentration, such as 10¹⁹-10²¹ cm⁻³, preferably10²⁰ cm⁻³.

If desired, an optional protective layer 4011, such as a protectivesilicon oxide layer, is formed on the surface of the first gate layer4009. Layer 4011 may have any appropriate thickness, such as, forexample 3-10 nm, preferably 5 nm. Materials other than silicon oxide maybe used for layer 4011, if desired.

A sacrificial blocking layer 4013 is then deposited over the protectivelayer 4011.

In a preferred aspect of the first embodiment, the blocking layer ismade of any conductive or insulating material which may be selectivelyetched with respect to other layers of the device. Preferably, theblocking layer 4013 comprises a silicon nitride layer. The blockinglayer may have any thickness. Preferably the blocking layer 4013 has thethickness that is desired for the whole control gate or an upper part ofa control gate, as will be described in more detail below. For example,layer 4013 has a thickness of 100 to 250 nm, preferably 160 nm. FIG. 37shows the device cross section at this stage of processing.

Next, a bit line pattern is transferred to the in process device waferor substrate using a reverse bit line mask, as shown in FIG. 38. In thismask, clear areas define the bit lines, and the opaque (i.e., dark)areas define the space between the bit lines. For example, a positivephotoresist layer (not shown in FIG. 38) is formed over the blockinglayer 4013 and then exposed through the reverse bit line mask anddeveloped. Of course, if a negative photoresist is used, then the clearand the opaque areas of the mask are reversed.

The mask features are etched into the blocking nitride 4013, theprotective oxide 4011, and the first gate layer 4009, using thephotoresist layer as a mask, to form a plurality of gate stacks 4015.The ONO dielectric 4007 serves as an etch stop layer. Then, thephotoresist layer is stripped from the patterned gate stacks 4015. Thephotoresist may be removed after the blocking nitride 4013 is etched, inwhich case the nitride may be used as a hard mask for etching the firstgate layer 4009. The gate stacks 4015 include a patterned first gateelectrode 9, an optional protective oxide 4011 and a patterned blockinglayer 4013. If desired, a thin layer of silicon nitride, oxynitiride oroxide is grown to seal the first gate electrode 4009 sidewalls.

Transistor source and drain regions 4017 are formed by self-aligned ionimplantation, using the gate stacks 4015 as a mask. The photoresistlayer may be left on the gate stacks during this implantation or removedprior to the implantation. The ion implantation is carried out throughthe ONO dielectric 4007. However, if desired, the portions of the ONOdielectric 4007 between the gates 4009 may be removed prior to the ionimplantation.

Channel regions 4019 of the active layer 4005 are located below the gateelectrodes 4009. The regions 4017 are doped with a second conductivitytype dopant different from the first conductivity type dopant of thechannels 4019. Thus, if the channels 4019 are p-type doped, then thesource and drain regions 4017 are n-type doped, and vice-versa. FIG. 38shows the device at this stage in the processing.

It should be noted that in a memory array, the designations “source” and“drain” are arbitrary. Thus, the regions 4017 may be considered to be“sources” or “drains” depending on which bit line a voltage is provided.Furthermore, since no field oxide regions are preferably used in thismemory array, each region 4017 is located between two gate electrodes4009. Therefore, a particular region 4017 may be considered to be a“source” with respect to one gate 4009, and a “drain” with respect tothe other gate 4009.

Next, gate stack sidewall spacers 4021 are formed on the sidewalls ofthe gate stacks 4015, as shown in FIG. 39. Preferably, the spacers 4021comprise silicon oxide, if the blocking layer 4013 comprises siliconnitride. However, the spacers may comprise any material which allows theblocking layer 4013 material to be selectively etched withoutsubstantially etching the spacers 4021. For example, the spacers 4021may comprise silicon nitride if the blocking layer 4013 comprisessilicon oxide. The spacers 4021 are preferably formed by conformaldeposition of a silicon oxide layer over the stacks 4015, followed by ananisotropic oxide etch. The spacer etch process concludes with an etchprocess for the ONO dielectric to expose the source and drain regions4017. Doping in the source and drain regions 4017 may be increased atthis time by additional self-aligned ion implantation, using the gatestacks 4015 and spacers 4021 as a mask, if desired. If so, theimplantation before spacer formation may be used to form lightly dopedsource/drain (LDD) extensions.

The salicide process is then used to form silicide regions 4023 in thesilicon source and drain regions 4017 in a self-aligned fashion. Thesalicide process comprises three steps. First a layer of metal, such asTi, W, Mo, Ta, etc., or a transition metal such as Co, Ni, Pt or Pd isblanket deposited over the exposed regions 4017, the sidewall spacers4021 and the blocking layer 4013 of the gate stacks 4015. The device isannealed to perform a silicidation by direct metallurgical reaction,where the metal layer reacts with the silicon in regions 4017 to formthe silicide regions 4023 over regions 4017. The unnreacted metalremaining on the spacers 4021 and the blocking layer 4013 is removed bya selective etch, e.g., by a piranha solution. The silicide regions 4023and the doped silicon regions 4017 together comprise the bit lines 4025.FIG. 39 shows the device at this stage in fabrication.

A conformal insulating layer 4027 is then deposited to fill the trenchesabove the bit lines 4025 and between the sidewall spacers 4021. Theinsulating layer 4027 may comprise any insulating material, such assilicon oxide, silicon oxynitride, PSG, BPSG, BSG, spin-on glass, apolymer dielectric layer (such as polyimide, etc.), and/or any otherdesired insulating material that is different than the material of theblocking layer 4013. The insulating layer 4027 is then planarized usingchemical-mechanical polishing (CMP), etch back and/or any other means toexpose the upper surface of the silicon nitride blocking layer 4013 onthe gate stacks 4015. FIG. 40 shows the device after the planarizationstep.

Next, the blocking silicon nitride layer 4013 is etched selectivelywithout substantially etching the spacers 4021 and the insulating layer4027. The protective oxide layer 4011, if present, is then removed byetching it from the upper surface of the first gate electrodes 4009 inthe stacks 4015. These etching steps form a gate contact via 4029 aboveeach gate 4009, as shown in FIG. 41. The width of the gate contact via4029 is substantially the same as the width of the first gate electrode4009 because the via sidewalls are the inner sidewalls of the sidewallspacers 4021. Therefore, the gate contact vias 4029 are self aligned tothe gates 4009 because the vias 4029 are bounded by the sidewall spacers4021 which extend above the gates 4009. No photolithographic maskingsteps are needed to form the gate contact vias 4029.

A second gate electrode conductive material 4031 is then deposited overthe entire device, as shown in FIG. 42. Preferably, the material 4031comprises a multilayer stack comprising a first n⁺-doped polysiliconlayer 4033, a silicide layer 4035 (such as a TiSi or WSi, etc) and asecond n⁺-doped polysilicon layer 4037. The polysilicon layers 4033 and4037 are preferably 100-300 nm thick, such as 200 nm thick. The silicidelayer 4035 is preferably 50 to 100 nm thick, such as 60 nm thick.Alternatively, the second gate material can also be formed from a singlelayer of silicide, metal, or any other combination of heavily dopedamorphous or polycrystalline silicon, silicide, and metal that makes agood ohmic contact with the first gate electrodes 4009.

Next, a photoresist layer (not shown) is applied over the material 4031and is exposed through the word line mask and developed. The photoresistlayer is used as a mask to etch the second gate electrode material 4031to form a plurality of word lines 4041. The ONO stack 4007 and theexposed active area layer 4005 are then etched using the word lines 4041as a mask. The photoresist layer may be left on the word lines 4041during this etching step or it may be removed prior to this etchingstep. The bottom insulating layer 4003 under the active area layer 4005and the intergate insulating layer 4027 over the bit lines 4025 serve asetch stop layers. Thus, the second gate electrode material 4031 ispatterned into a plurality of word lines 4041 which overlie theintergate insulating layer 4027 as shown in FIG. 43, and into upperportions 4043 of the first gate electrodes, where the material 4031extends into the vias 4029, as shown in FIG. 44. FIG. 43 is a crosssection along line A-A in FIG. 42 and FIG. 44 is a cross section alongline B-B in FIG. 42. Therefore, the word lines 4041 are self aligned tothe control gates 4009/4043, since a photolithography step is notrequired to align the word lines to the gates.

If desired, the exposed active area 4005 and gate electrode 4009/4043sidewalls may be optionally sealed by growing a thin layer of siliconnitride or oxide on them, for example by thermal nitridation oroxidation. This completes construction of the memory array. Aninsulating layer is then deposited, and if necessary planarized, overthe word lines 4041.

The word line photolithography step does not require misalignmenttolerances, since the word lines are patterned using the same mask asthe charge storage regions 4007 and the active layer 4005 (i.e., channelregions 4019) of each TFT in the cell. Therefore, the word lines 4041are not only self aligned to the control gate 4009/4043 of the TFTEEPROM by being deposited in the self aligned vias 4029, but the wordlines 4041 are also self aligned to the charge storage regions 4007 andthe channel regions 4019 of each memory cell. By using a fully selfaligned memory cell, the number of expensive and time consumingphotolithography steps is reduced. Furthermore, since no misalignmenttolerances for each cell are required, the cell density is increased.Another advantage of the device of the first embodiment is that since athick intergate insulating layer 4027 is located between the bit lines4025 and the word lines 4041, the parasitic capacitance and a chance ofa short circuit between the bit lines and the word lines are decreased.

FIGS. 45 and 46 illustrate a method of making a TFT EEPROM nonvolatileflash memory array according to the second preferred embodiment of thepresent invention. The method of the second preferred embodiment is thesame as that of the first embodiment illustrated in FIGS. 37-44, exceptthat the sacrificial blocking layer 4013 is omitted.

FIG. 45 illustrates an in-process semiconductor device 4100 according tothe second preferred embodiment. The device 4100 illustrated in FIG. 45is at the same stage in processing as the device 4001 in FIG. 40. Thedevice 4100 contains the interlayer insulating layer 4103, the activelayer 4105, the charge storage region 4107 (e.g., an ONO stack orisolated nanocrystals), source and drain regions 4117, channel regions4119, silicide regions 4123 and bit lines 4125.

The gate electrode 4109 of the device 4100 is made thicker than the gateelectrode 4009 in the first embodiment. For example, the gate electrode4109 may have any appropriate thickness, such as 160 to 360 nm,preferably 260 nm. Since the blocking 4013 layer is omitted, the gatesidewall spacers 4121 are formed on the patterned gate electrode 4109covered by a protective silicon oxide layer (not shown) after theformation of the source and drain regions 4117. The sidewall spacers4121 extend to the top of the gate electrode 4109. The silicide regions4123 are then formed on the source and drain regions 4117 by depositinga metal layer and reacting the metal layer with the source and drainregions 4117. No silicide is formed on the gate electrode 4109, which iscovered by the silicon oxide protective layer, and on the sidewallspacers 4121. The insulating layer 4127 is then deposited between thesidewall spacers 4121 and over the gate electrodes 4109. Preferably, thelayer 4127 is silicon oxide, but may comprise any other insulatingmaterial, as in the first embodiment. Layer 4127 is then planarized toexpose the upper surface of the gate electrode 4109. The insulatinglayer 4127 is preferably planarized by CMP, but may be planarized byetch back and/or any other means. During the planarization, theprotective silicon oxide layer is also removed to expose the uppersurface of the gate electrode 4109, as shown in FIG. 45.

Since the selective nitride blocking layer 4013 etch step is notperformed in the second embodiment, the spacers 4121 may be composed ofsilicon nitride, rather than silicon oxide. Silicon nitride spacers areadvantageous because they conform to the underlying topography betterthan oxide spacers. The spacers 4121 and the gate 4109 may act as apolish or etch stop during the planarization of layer 4127.

After the gate electrodes 4109 are exposed, the memory array of thesecond preferred embodiment is completed just like the array in thefirst preferred embodiment. As in the first embodiment, one or moreconductive layers is/are deposited directly over the tops of thesidewall spacers 4121 and exposed gate electrodes 4109. For example, theconductive layers may comprise a silicide 4135 layer between polysiliconlayers 4133 and 4137. As shown in FIG. 46, the conductive layer(s)is/are then patterned to form a plurality of word lines 4141, whichcontact the exposed gate electrodes 4109. During the same patterningstep, the charge storage region 4107 and the active layer 4105 are alsopatterned, as in the first embodiment. Therefore, the word lines 4141are self aligned to the control gate electrodes 4109, since aphotolithography step is not required to align the word lines to thegates.

If desired, the exposed active area 4105 and gate electrode 4109sidewalls may be optionally sealed by growing a thin layer of siliconnitride or oxide on them, for example by thermal nitridation oroxidation. This completes construction of the memory array. Aninsulating layer is then deposited, and if necessary planarized, overthe word lines 4141.

The word line photolithography step does not require misalignmenttolerances, since the word line is patterned using the same mask as thecharge storage regions 4107 and the active layer 4105 of each TFT in thecell. Therefore, the word lines 4141 are not only self aligned to thecontrol gate 4109 of the TFT EEPROM by being deposited directly over theexposed upper surfaces of the gates 4109 and spacers 4121, but the wordlines 4141 are also self aligned to the charge storage regions 4107 andthe channel regions 4119 of each memory cell. By using a fully selfaligned memory cell, the number of expensive and time consumingphotolithography steps is reduced. Since no misalignment tolerances arerequired, the cell density is increased. Furthermore, eliminatingblocking nitride deposition and selective etch steps of the firstembodiment, reduces the step count by three, which simplifies theprocess flow.

FIG. 47 illustrates a TFT EEPROM nonvolatile flash memory array 4200according to the third preferred embodiment of the present invention.The device and method of the third preferred embodiment are the same asthat of the first or the second embodiments illustrated in FIGS. 37-46,except that the charge storage region comprises an electrically isolatedfloating gate rather than the ONO stack or isolated nanocrystals as inthe first or the second preferred embodiment.

As shown in FIG. 47, the non-volatile transistor (i.e., the TFT EEPROM)is constructed as a floating-gate field effect transistor. In this case,the dielectric triple layer consisting of the ONO stack or the oxidelayer containing electrically isolated nanocrystals is replaced with atunnel dielectric, such as tunnel silicon oxide layer 4206. The tunneloxide 4206 has a thickness of 5 to 10 nm, preferably 7 nm. The tunneloxide layer 4206 is formed over the active area 4205, as in the firstand second embodiments.

The first gate electrode 4209 is formed and patterned on the tunneloxide layer 4206, as in the first and second embodiments. However, inthe third embodiment, the first gate electrode 4209 comprises a floatinggate rather than a control gate. The floating gate 4209 is self-alignedto the transistor channel 4219, as in the first and second embodiments.

The device illustrated in FIG. 47 is at the same stage in processing asthe device in FIG. 42. The device contains the substrate 4203, thesource and drain regions 4217, channel regions 4219, sidewall spacers4221 adjacent to floating gate 4209 sidewalls, silicide regions 4223,bit lines 4225 and insulating layer 4227.

The other deviation from the first and second embodiments is theformation of a control gate dielectric 4212 over the floating gate 4209,as shown in FIG. 47. The control gate dielectric may have anyappropriate thickness, such as 8 to 20 nm, preferably 12 nm. The controlgate dielectric 4212 may be grown on the control gate by thermaloxidation or deposited by CVD or other means. The control gatedielectric may comprise silicon oxide, silicon nitride, siliconoxynitride, or an ONO stack. The control gate 4243 and word lines 4241are then deposited and patterned over the control gate dielectric 4212as in the first and second preferred embodiments to complete the deviceshown in FIG. 47. The control gate dielectric 4212 and the control gate4243 are located inside the sidewall spacers 4221.

FIGS. 48A-C and 49A-C illustrate two alternative preferred methods ofmaking one TFT (i.e., one cell) in the device 4200 shown in FIG. 47.According to the first preferred method, a gate stack 4215 comprising afloating gate 4209, a protective layer 4211 and an optional sacrificialblocking layer 4213 are formed over the tunnel dielectric 4206. Thesource and drain regions 4217 are implanted into the active area 4205using the gate stack 4215 as a mask, such that a channel region 4219 isformed below the tunnel dielectric 4206. Then, sidewall spacers 4221 areformed over the gate stack 4215. An insulating layer 4227 is formedadjacent to the spacers and planarized to expose the blocking layer4213, as shown in FIG. 48A.

Then, as shown in FIG. 48B, the protective layer 4211 and the blockinglayer 4213 are removed by etching. This forms the gate contact via 4229.The via 4229 sidewalls are the sidewall spacers 4221 which extend abovethe floating gate 4209.

A control gate dielectric 4212 is then formed, for example, by thermaloxidation, on the exposed floating gate 4209 inside the via 4229 asshown in FIG. 48C. Then, one or more conductive layers are depositedover the gate contact via 4229 and the insulating layer 4227. Theselayer(s) are patterned to form a control gate 4243 in the via 4229 and aword line 4241 above layer 4227. The control gate dielectric 4212separates the control gate 4243 from the floating gate 4209.

According to the second preferred method, a gate stack 4215 comprising afloating gate 4209, the control gate dielectric 4212 and a sacrificialblocking layer 4213 are formed over the tunnel dielectric 4206. Thesource and drain regions 4217 are implanted into the active area 4205using the gate stack 4215 as a mask, such that a channel region 4219 isformed below the tunnel dielectric 4206. Then, sidewall spacers 4221 areformed over the gate stack 4215. An insulating layer 4227 is formedadjacent to the spacers and planarized to expose the blocking layer4213, as shown in FIG. 49A.

Then, as shown in FIG. 49B, the blocking layer 4213 is removed byetching to expose the control gate dielectric 4212. This forms the gatecontact via 4229. The via 4229 sidewalls are the sidewall spacers 4221which extend above the floating gate 4209 and the dielectric 4212. Theblocking layer 4213 may consist of a heavily doped polysilicon, in whichcase it may be left in the via 4229, if desired.

As shown in FIG. 49C, one or more conductive layers are deposited overthe gate contact via 4229 and the insulating layer 4227. These layer(s)are patterned to form a control gate 4243 in the vias 4229 and a wordline 4241 above layer 4227. The control gate dielectric 4212 separatesthe control gate 4243 from the floating gate 4209.

In the methods of FIGS. 48A-C and 49A-C, the word line 4241 is selfaligned to the control gate 4243, to the control gate dielectric 4212and to the floating gate 4209.

FIG. 50 illustrates a TFT EEPROM nonvolatile flash memory array 4300according to a first preferred aspect of the fourth preferred embodimentof the present invention. The device and method of the fourth preferredembodiment is the same as that of the third preferred embodimentillustrated in FIG. 47, except that the control gate dielectric islocated above the sidewall spacers. Furthermore, the blocking layer 4213is omitted. As shown in FIG. 50, the sidewall spacers 4221 extend to thetop of the floating gate 4209, similar to the device of the secondpreferred embodiment. The control gate dielectric 4212 is deposited overthe floating gates 4209, the sidewall spacers 4221, and the insulatinglayer 4227. The word line 4241 is then deposited and patterned over thecontrol gate dielectric 4212, as in the first and second preferredembodiments. In the device of FIG. 50, the word line 4241 acts both as aword line and as a control gate. Thus, a separate control gate may beomitted. The word line 4241 is self aligned to the floating gates 4209.The word line 4241 may comprise one or more layers, such as the silicidelayer 4235 between polysilicon layers 4233 and 4237.

FIG. 51 illustrates a TFT EEPROM nonvolatile flash memory array 4300according to the second preferred aspect of the fourth preferredembodiment of the present invention. The device and method of thispreferred aspect are the same as those illustrated in FIG. 50, exceptthat an upper portion of the floating gate extends above the sidewallspacers. The device illustrated in FIG. 51 is at the same stage inprocessing as the device in FIGS. 47 and 50. As shown in FIG. 51, thedevice contains the interlayer insulating layer 4303, the tunneldielectric 4306, the source and drain regions 4317, channel regions4319, silicide regions 4323, bit lines 4325 and insulating layer 4327.

The device illustrated in FIG. 51 includes the processing stepsillustrated in FIGS. 48A-B and described above. Thus, a lower portion ofthe floating gate 4309 is exposed in a gate contact via 4329 between thesidewall spacers 4321 which extend above the lower portion of thefloating gate, similar to that shown in FIG. 48B. However, instead offorming a control gate dielectric 4312 in the via 4329, an upper portionof the floating gate 4310 is deposited in the via. The upper portion ofthe floating gate 4310 is formed by depositing a conductive layer, suchas a doped polysilicon layer, over the vias 4329, the spacers 4321 andthe insulating layer 4327, such that it contacts the exposed lowerportion of the floating gate 4309 in the via 4329. The conductive layeris patterned using photolithography into an upper floating gate portion4310 such that it extends vertically above the sidewall spacers 4321.Preferably, the conductive layer also extends horizontally above thespacers 4321. Thus, the upper gate portions 4310 have a “T” shape. Then,the control gate dielectric 4312 is formed on the exposed upper surfaceof the upper portion of the floating gate 4310 by thermal growth, CVDand/or various other deposition techniques (such as sputtering, etc.).One or more conductive layers 4333, 4335, 4337 are then deposited overthe control gate dielectric 4312 and are patterned into word lines 4341.The conductive layers may be, for example, a silicide layer 4335sandwiched between doped polysilicon layers 4333, 4337, as in the firstpreferred embodiment. In the fourth preferred embodiment, the word lines4341 serve as the control gates of the TFTs. Since the top surface ofthe floating gate 4309/4310 in the fourth embodiment is larger than inthe third embodiment, the area between the floating gate and the controlgate/word line is increased in the TFT of the fourth embodiment comparedto the third embodiment. The increase in area between the floating gateand the control gate/word line is advantageous because it increases thecapacitive coupling between the floating gate and the control gate/wordline.

In a preferred aspect of the fourth embodiment, the top surface of theupper portion of the floating gate 4310 is textured or roughened tofurther increase the capacitive coupling between the floating gate andthe control gate/word line. For example, at least the upper portion ofthe floating gate 4310 may be made of hemispherical grain silicon (HSG),or the upper surface of the floating gate may be roughened by etching orcoarse polishing. In other words, the upper portion of the floating gatemay be textured or roughened similar to the texturing or rougheningmethods used to texture or roughen bottom conductive plates of DRAMcapacitors.

While the first through fourth preferred embodiments describe andillustrate a TFT EEPROM nonvolatile flash memory array, the presentinvention should not be considered to be so limited. For example, ratherthan a self aligned word line in a TFT EEPROM array, any gate line maybe self aligned to a MOSFET (i.e., metal oxide semiconductor fieldeffect transistor) gate according to the preferred embodiments of thepresent invention. Furthermore, the EEPROM array may be formed in a bulksilicon substrate rather than over an interlayer insulating layer.

The first through the fourth preferred embodiments describe andillustrate a cross-point array of word lines and bit lines at ahorizontal level and a method of making thereof. Each memory cellconsists of a single programmable field effect transistor (i.e., TFT),with its source and drain connected to the j^(th) bit line and the(j+1)^(st) bit line, respectively, and a control gate being eitherconnected to or comprising the k^(th) word line. This memory arrangementis known as the NOR Virtual Ground (NVG) Array (also referred to asVGA). If desired, the memory array may also be arranged in non volatileflash memory architectures other than VGA, such as NOR-type memory orDual String NOR (DuSNOR) memory, for example. The DuSNOR architecture,where two adjacent cell strings share a common source line but usedifferent drain lines, is described in K. S. Kim, et al., IEDM-95,(1995) page 263, incorporated herein by reference. The DuSNOR memory maybe fabricated using the same process as the VGA memory, except that anadditional masking step is used to pattern the active area layer toseparate the drain regions of adjacent cells. The process sequence ofthe first through third preferred embodiments of the present inventionrequires only two photolithographic masking steps.

One masking step is for gate patterning/self aligned bit line formation.The other masking step is for word line patterning. The methods of thepreferred embodiments of the present invention exploit self-alignment toreduce alignment tolerances between the masks. The memory cell areaachieved with the foregoing process is about 4 F², where F is theminimum feature size (i.e. 0.18 microns in a 0.18 micron semiconductorprocess). The term “about” allows for small deviations (10% or less) dueto non-uniform process conditions and other small deviations fromdesired process parameters. If the charge storage medium used in thetransistor is not conductive, e.g., it is formed from nitride oroxy-nitride (i.e. using the ONO charge storage medium), or electricallyisolated nanocrystals, the localized nature of charge storage can beexploited to store two bits per cell. In this case, the effective cellarea per bit equals about 2F².

The NVG array of the first through fourth preferred embodiments is verysuitable for vertical stacking of horizontal planar NVG arrays. FIG. 52illustrates a three dimensional memory array 4400 according to a fifthpreferred embodiment of the present invention. The three dimensionalmemory array contains a three dimensional array of TFT EEPROMs madeaccording to the first, second, third or fourth preferred embodiment.Each TFT EEPROM contains a channel 4419, source and drain regions 4417,a control gate 4443, control gate sidewall spacers (not shown forclarity in FIG. 52) and a charge storage region 4407 between the channeland the control gate 4409. The charge storage region may comprise an ONOdielectric, isolated nanocrystals or a floating gate.

The memory array also contains a plurality of bit line columns 4425,each bit line contacting the source or the drain regions 4417 of aplurality of TFT EEPROMs. The columns of the bit lines 4425 extendsubstantially perpendicular to the source-channel-drain direction of theTFT EEPROMs (i.e., a small deviation from the perpendicular direction isincluded in the term “substantially perpendicular”). It should be notedthat the columns of the bit lines 4425 may extend substantiallyperpendicular to the source-channel-drain direction of the TFT EEPROMsthroughout the entire array 4400 or only in a portion of the array 4400.The bit lines in each device level are shaped as rails which extendunder the intergate insulating layer. The bit lines include the burieddiffusion regions formed during the source and drain doping steps andthe overlying silicide layers. The source and drain regions are formedin the bit lines where the word lines intersect (i.e., overlie) the bitlines and the doped regions are located adjacent to the EEPROM channelregions.

The memory array also includes a plurality of word line rows 4441. Eachword line contacts the control gates 4443 of a plurality TFT EEPROMs4400 (or the word lines comprise the control gates). The rows of wordlines extend substantially parallel to the source-channel-draindirection of the TFT EEPROMs (i.e., a small deviation from the paralleldirection is included in the term “substantially parallel”). It shouldbe noted that the rows of the word lines 4441 may extend substantiallyparallel to the source-channel-drain direction of the TFT EEPROMsthroughout the entire array 4400 or only in a portion of the array 4400.The plurality of word lines 4441 are self aligned to the control gates4443 of the array of TFT EEPROMs (or the word lines themselves comprisethe control gates). If floating gates, but not control gates areincluded in the array, then the word lines are self aligned to thefloating gates and to the control gate dielectric.

Each device level 4445 of the array is separated and decoupled in thevertical direction by an interlayer insulating layer 4403. Theinterlayer insulating layer 4403 also isolates adjacent word lines 4441and adjacent portions of the active areas 4405 below the respective wordlines 4441 in each device level 4445. The effective cell area per bit inthe resulting three dimensional memory array is about 2F²/N, where N isthe number of device levels (i.e., N=1 for a two dimensional array andN>1 for a three dimensional array). The array of nonvolatile memorydevices 4400 comprises a monolithic three dimensional array of memorydevices. The term “monolithic” means that layers of each level of thearray were directly deposited on the layers of each underlying level ofthe array. In contrast, two dimensional arrays may be formed separatelyand then packaged together to form a non-monolithic memory device.

Each cell in one level 4445 of the memory array can be formed using onlytwo photolithographic masking steps. However, additional masking stepsmay be needed to form contacts to the bit lines 4425. In a sixthpreferred embodiment of the present invention, a conductive layer isformed over the array of memory devices. The conductive layer is thenpatterned to form a plurality of word lines or word line contact layersand at least one bit line contact layer which contacts at least one ofthe plurality of the bit lines. Thus, a separate bit line contactdeposition and patterning step may be avoided, since the same conductivelayer may be patterned to form the word lines/word line contacts and thebit line contacts. Of course, if desired, the word lines/word linecontacts and the bit line contacts may be made from different materialsand/or patterned using different masks.

FIG. 53 illustrates a bit line contact 4447 according to one preferredaspect of the sixth preferred embodiment. In FIG. 53, a first dopedpolysilicon layer 4433 is formed over the inter-gate insulating layer4427. A bit line contact via 4449 is then formed in the insulating layer4427 in which a top portion of the bit line 4425 is exposed. A silicidelayer 4435 and a doped polysilicon layer 4437 are then deposited, suchthat the silicide layer 4435 contacts the bit line 4425 through the viahole. The layers 4433, 4435 and 4437 are then photolithographicallypatterned using the same mask to form both the plurality of word lines4441 and a plurality of bit line contacts 4447. An upper interlayerinsulating layer 4403 is then formed over the word lines 4441 and bitline contacts 4447. Word line contact vias 4451 and bit line contactlayer contact vias 4453 are formed in the insulating layer 4403 forformation of further contacts. It should be noted that the word lines4441 and the bit line contact layer 4447 are not limited to thematerials described. The layers 4441 and 4447 may comprise one or morepolysilicon, silicide or metal layers. Furthermore, while the gate line4441 and the contact 4447 are located in the same level of the device,the contact 4447 may extend into a lower level of the array to contact abit line or a word line in the lower level of the array, if desired.

FIG. 54 illustrates a bit line contact 4547 according to anotherpreferred aspect of the sixth preferred embodiment. In this embodiment,at least one bit line contact via 4549 extends through at least oneinterlayer insulating layer 4503 between different levels of the array.In FIG. 54, the word line 4541 is first patterned and an interlayerinsulating layer 4503 is deposited thereon. Word line contact vias 4551and bit line contact vias 4549 are formed in the insulating layer 4503.The bit line contact via 4549 extends through the intergate insulatinglayer 4527 to the bit line 4525, which comprises the doped region 4417and the silicide region 4423.

Then one or more conductive layers, such as silicide layer 4555 anddoped polysilicon layer 4557 are deposited on the interlayer insulatinglayer 4503 and in the vias 4551 and 4549. The one or more conductivelayer(s) 4555, 4557 are then photolithographically patterned using thesame mask to form both a word line contact 4559, the bit line contact4547, and plurality of word lines in the memory layer above the memorylayer shown.

The word line and bit line contacts can reach down to lower levels,e.g., every other lower level, or several lower levels at the same time.Thus, in FIG. 54, the bit line contact 4547 and the word line contact4559 are formed in the N+1 level of the array, and extend to the wordlines 4541 and the bit lines 4525 in the Nth level of the array. Theword line contacts and bit line contacts connect the word lines and thebit lines with the peripheral circuits located in the semiconductorsubstrate below the first device level of the array (or locatedelsewhere in the array, such as above or within the array, butpreferably at least in part vertically integrated or aligned with thearray). Landing pads are made in level N+1 conductor for the next levelcontacts.

FIGS. 55 through 61 illustrate a method of making a TFT EEPROMnonvolatile flash memory array according to the seventh preferredembodiment of the present invention. The method of the seventh preferredembodiment starts in the same way as that of the first, second, third,or fourth embodiments illustrated in FIGS. 37-51, except that asacrificial dummy block which holds the place of the gate electrode isused in the process. A transistor formed by this method is called areplacement-gate transistor. The array made by the seventh preferredembodiment may be formed as three dimensional array shown in FIG. 52,having an effective cell area per bit of about 2F²/N.

As in the previously described embodiments, the process starts with adeposition of a semiconductor active area, such as an amorphous siliconor polycrystalline silicon layer 4605 over an interlevel insulatinglayer 4603, as shown in FIG. 55. Then, a plurality of sacrificial dummyblocks 4604 are formed over the active layer 4605, as shown in FIG. 56.The sacrificial dummy blocks 4604 may comprise one or more materials, atleast one of which may be selectively etched with respect to thematerial of an intergate insulating layer 4627 to be formed later. Forexample, if the intergate insulating layer 4627 comprises silicon oxide,then the dummy blocks may comprise silicon nitride, silicon oxynitride,polysilicon or other materials which may be selectively etched withrespect to silicon oxide.

Preferably, the active layer 4605 comprises amorphous silicon and thedummy blocks 4604 are formed of a material which is deposited at atemperature below 600° C. to avoid recrystallizing the amorphous siliconlayer 4605 into a polysilicon layer with a small grain size. Forexample, the dummy blocks 4604 may be formed by depositing a lowtemperature PECVD silicon nitride layer over the active layer 4605 andpatterning the silicon nitride layer into a plurality of dummy blocks4604 using photolithography.

In a preferred aspect of the seventh embodiment, the dummy blocks 4604comprise a plurality of layers, including a sacrificial channeldielectric layer 4667, a sacrificial gate layer 4669, and a protectiveoxide layer 4671, as shown in FIG. 55. Layers 4669 and 4671 arepatterned using a reverse bit line mask, similar to that illustrated inFIG. 38 of the first preferred embodiment, to form the dummy blocks4604, as shown in FIG. 56. Since all layers 4667, 4669, 4671 above theactive layer are sacrificial, lower quality materials may be used forthese layers. For example, low temperature silicon oxide (LTO) or PECVDsilicon oxide may be used for the channel dielectric layer 4667. Thus,layer 4667 may be deposited at a low temperature (i.e., below 600° C.)to avoid recrystallizing the amorphous silicon active layer 4605 into apolysilicon layer with a small grain size. If desired, all layers of thedummy blocks 4604 may be deposited at temperatures below 600° C. In thiscase, the amorphous state of layer 4605 is preserved until a subsequentsalicide formation on the source and drain regions 4617. The silicide4623 on the source and drain regions 4617 may act as a catalyst forlateral crystallization of amorphous silicon in the source and drainregions 4617 to form a polycrystalline silicon active layer 4605 with alarge grain size.

Subsequently, TFT source and drain regions 4617 are implanted into theactive layer 4605 using the dummy blocks as a mask. The channel layers4619 are located in layer 4605 between regions 4617 and below the blocks4604. If the dummy blocks 4604 contain a polysilicon layer, thenpreferably, sidewall spacers 4621 are formed on the dummy block 4604sidewalls to separate silicide from the source/drain junctions, toprevent subsequent silicide formation on the dummy blocks and toincrease flexibility in source/drain engineering. The spacers 4621 maybe composed of silicon oxide or silicon nitride, or two differentlayers, as shown in FIG. 57. If desired, an additional implantation maybe performed into the source and drain regions 4617 using the blocks4604 and spacers 4621 as a mask. If the dummy blocks 4604 do not containpolysilicon (i.e., are composed of silicon nitride), then the spacers4621 may be omitted.

A metal layer, such as Ti, W, Mo, Ta, etc., or a transition metal suchas Co, Ni, Pt or Pd is blanket deposited over the exposed regions 4617and the dummy blocks 4604. The device is annealed to perform asilicidation by direct metallurgical reaction, where the metal layerreacts with the silicon in regions 4617 to form the silicide regions4623 over regions 4617, as shown in FIG. 58. The unnreacted metalremaining on the dummy blocks 4604 is removed by a selective etch, e.g.,by a piranha solution. The active layer 4605 is then recrystallized bylaser or thermal annealing using the silicide regions 4623 as acatalyst. Alternatively, if desired, the active layer 4605 may berecrystallized simultaneously with the silicide 4623 formation, or theactive layer 4605 may be recrystallized by laser or thermal annealingbefore the formation of the dummy blocks 4604.

After the formation of the buried bit lines 4625 which contain thesource and drain regions 4617 and the silicide 4623 regions, a conformalintergate insulating layer 4627 is deposited between and above the dummyblocks 4604. Preferably, layer 4627 comprises silicon oxide (HDP oxide),as in the other preferred embodiments. The layer 4627 is then planarizedby CMP and/or etchback to expose the top portions of the dummy blocks4604. For example, if the dummy blocks 4604 contain a silicon oxideprotective layer 4671 and silicon oxide spacers 4621, then these layersmay be removed together with the top portion of layer 4627 duringplanarization. In this case, the top portions of the sacrificial gates4669 are exposed after planarization, as shown in FIG. 58.

Next, the dummy blocks 4604 are selectively etched (i.e., removed)without substantially etching the intergate insulating layer 4627. Forexample, if the dummy blocks 4604 include the sacrificial polysilicongates 4609, then these sacrificial gates 4609 are selectively etchedwithout substantially etching the spacers 4621 and the intergateinsulating layer 4627. If the dummy blocks include a sacrificial gatedielectric layer 4667, then this layer 4667 can be removed using plasmaetch back or wet etch methods. As shown in FIG. 59, a plurality of vias4629 are formed in locations where the dummy blocks 4604 were previouslylocated.

After the surface of the active layer 4605 above the channel regions4619 is exposed by removing the dummy block materials, the “real” orpermanent gate dielectric material is immediately grown and/or depositedon the exposed regions. Preferably, this dielectric comprises a chargestorage region 4607 selected from the ONO triple layer or the pluralityof electrically isolated nanocrystals, as shown in FIG. 60.Alternatively, this dielectric may comprise a tunnel dielectric 4606 ifthe TFT EEPROM contains a floating gate 4609, as shown in FIG. 61. Thecharge storage layer 4607 is located on the bottom of the vias 4629above the channel regions 4619. The charge storage layer 4607 alsocontains vertical portions located on the sidewalls of the intergateinsulating layer 4627 (or on the sidewalls of the spacers 4621, if thespacers are present) and horizontal portions located above the intergateinsulating layer 4627, as shown in FIG. 60.

Subsequently, a conductive material is deposited over the intergateinsulating layer 4627 and the charge storage regions 4607. Theconductive material may comprise polysilicon or a combination ofpolysilicon 4633, 4637 and silicide 4635 layers, as in the otherembodiments. The conductive material fills the vias 4629 and overliesthe charge storage layer 4607. The conductive material is then patternedto form a plurality of word lines 4641, as in the other embodiments. Theactive layer 4605 and the charge storage layer 4607 is then patternedusing the word lines 4641 as a mask as in the other embodiments. Theportions of the word lines 4641 located in the vias 4629 comprise thecontrol gates 4609 of the TFT EEPROMs, as shown in FIG. 60. If afloating gate TFT EEPROM is desired, then a floating gate 4609 and acontrol gate dielectric 4612 may be formed in the vias 4629 prior toforming the control gates/word lines 4641, as shown in FIG. 61.

In an eighth preferred embodiment of the present invention, the TFTs ina plurality of the levels of the three dimensional array of FIG. 52undergo a recrystallization and/or a dopant activation step at the sametime. This reduces the device fabrication time and cost. Furthermore, ifeach level of the array were subjected to a separate crystallizationand/or dopant activation annealing, then the lower levels would undergomore annealing steps than the upper levels. This may lead to device nonuniformity because the grain size may be larger in the active areas ofthe lower levels and/or the source and drain regions may have adifferent dopant distribution in the lower levels than in the upperlevels.

Thus, in a first preferred aspect of the eighth embodiment, amorphoussilicon or polysilicon active areas of TFTs in a plurality of levels arerecrystallized at the same time.

Preferably, TFTs in all levels are recrystallized at the same time. Therecrystallization may be effected by thermal annealing in a furnace orby rapid thermal annealing (RTA) in an RTA system. The thermal annealingmay be carried out at 550 to 800° C. for 6-10 hours, preferably at 650to 725° C. for 7-8 hours.

Furthermore, since a silicide layer 4423 contacts the source and drainregions 4417, the silicide may act as a catalyst for recrystallization,especially if nickel, cobalt or molybdenum silicide is used. The metalatoms diffuse though the active areas of the TFTs, leaving behind largegrains of polysilicon. Thus, recrystallizing the amorphous silicon orpolysilicon active areas after depositing the bit line metallizationleads to larger grains and allows the use of lower recrystallizationtemperatures, such as 550 to 650° C. Furthermore, no separate metaldeposition and patterning for metal induced crystallization is required.Thus, each level of the array may be subjected to a recrystallizationanneal after the bit line metallization is formed for this level.Alternatively, all levels of the array may be subjected to arecrystallization anneal after the bit line metallizations for everylevel of the array have been formed. Furthermore, in an alternativeaspect of the eighth embodiment, silicide formation step and therecrystallization steps may be carried out during the same annealingstep for each level of the array.

In a second preferred aspect of the eighth embodiment, the doped regionsin a plurality of levels are activated at the same time. Preferably, thedoped regions in all of the levels are activated at the same time. Thedoped regions comprise the TFT source and drain regions as well as anyother doped region formed in the three dimensional array. Preferably,the doped regions are activated by subjecting the array to an RTAtreatment. However, if desired, the activation may be carried out bythermal annealing at about 700 to about 850° C. for 20 to 60 minutes.The activation may be carried out before or after the crystallizationanneal.

In a third preferred aspect of the eighth embodiment, therecrystallization and dopant activation are carried out in the sameannealing step of a plurality of levels or for all the levels of thearray. The annealing step should be conducted at a sufficiently hightemperature and for a sufficient length of time to activate the dopantsand to recrystallize the TFT active areas, without causing the sourceand drain region dopants to diffuse into the channel regions of theTFTs. Preferably, the combined recrystallization and dopant activationannealing step comprises an RTA treatment.

In a fourth preferred aspect of the eighth embodiment, an extraphotolithographic masking step is provided to form crystallizationwindows used to deposit the crystallization catalyst material. Forexample, as shown in FIG. 62, the material 4722 used to form sidewallspacers 4721 is patterned using a separate photolithographic mask toform the crystallization windows 4701. Thus, in the replacement-gatetransistor method shown in FIGS. 55-61, the crystallization windows 4701are formed in the low temperature oxide (LTO) layer used to makesidewall spacers after the reverse bit line pattern is etched into theprotective oxide 4771 and the sacrificial gates 4769. Crystallizationmask features are etched into the oxide layer 4722 to clear the surfaceof the active layer 4705. Simultaneously, sidewall spacers 4721 areformed on the sacrificial gates 4769. Then, the photoresist (not shown)is stripped. FIGS. 63 and 64 illustrate cross-sections along lines A-Aand B-B in FIG. 62, respectively. If desired, the crystallizationwindows may also be added to the process of the first through the fourthembodiments. Such windows would be formed during the formation of thesidewall spacers in those embodiments.

Next, a catalyst, such as Ni, Ge, Fe, Mo, Co, Pt, Pd, Rh, Ru, Os, Ir,Cu, Au, a silicide thereof, or other transition metal elements or theirsilicides, is deposited. The catalyst comes in contact with theamorphous silicon active layer 4705 only in the open windows 4701. Thecatalyst material may be deposited as a solid layer or as a catalystsolution. Alternatively, the catalyst may be ion implanted or diffusedinto the active layer 4705. Then, the device is annealed for severalhours at a temperature below 600° C., preferably at 550° C. This lowanneal temperature is preferred to minimize spontaneous nucleation inthe amorphous silicon. Polysilicon grains in the present embodimentstart growing from the seed regions in the windows 4701 and growlaterally. At the completion of anneal, the grain boundaries 4702 arealigned as shown in FIG. 65. Then, the catalyst is removed. A solidcatalyst layer may be removed by selective etching, while catalyst atomsin the recrystallized polysilicon may be removed by gettering, such asby annealing the device in a chlorine containing gas. The LTO oxidelayer 4722, which comprises the boundaries of crystallization windows4701, is then removed by selective etching, and the device is completedas in the other embodiments. It should be noted that the word lines (WLin FIGS. 62 and 65) are subsequently formed over the regions where thecrystallization windows 4701 used to be formed. Since thecrystallization begins in the windows 4701, the grain boundaries 4702which are parallel to the word lines are located away from the windowregions, in the regions of the active layer 4705 between the word lines.These regions of the active layer 4705 between the word lines areremoved after the formation of the word lines. Therefore, since thechannel regions of the TFTs are located below the word lines, these TFTchannel regions contain fewer grain boundaries, and substantially nograin boundaries which are parallel to the word lines.

III. Rail Stack TFTs

The following preferred embodiments provide an array of TFTs with acharge storage region, such as EEPROM TFTs, arranged in a rail stackconfiguration. The embodiments described herein are in the context of anon-volatile reprogrammable semiconductor memory and methods offabrication and utilization thereof. Those of ordinary skill in the artwill realize that the following detailed description of the embodimentsof the present invention is illustrative only and is not intended to bein any way limiting. Other embodiments of the present invention willreadily suggest themselves to such skilled persons having the benefit ofthis disclosure. Reference will now be made in detail to implementationsof the present invention as illustrated in the accompanying drawings.The same reference indicators will be used throughout the drawings andthe following detailed description to refer to the same or like parts.

In the interest of clarity, not all of the routine features of theimplementations described herein are shown and described. It will, ofcourse, be appreciated that in the development of any such actualimplementation, numerous implementation-specific decisions must be madein order to achieve the developer's specific goals, such as compliancewith application- and business-related constraints, and that thesespecific goals will vary from one implementation to another and from onedeveloper to another. Moreover, it will be appreciated that such adevelopment effort might be complex and time-consuming, but wouldnevertheless be a routine undertaking of engineering for those ofordinary skill in the art having the benefit of this disclosure.

The present embodiment is directed to a two- or, more preferably, athree-dimensional many-times-programmable (MTP) non-volatile memory. Thememory provides a bit cell size of 2F²/N where F is the minimum featuresize (e.g., 0.18 microns in a 0.18 micron semiconductor process and 0.25microns in a 0.25 micron semiconductor process) and N is the number oflayers of devices in the third (i.e., vertical) dimension. Thus, for a0.18 micron process with 8 devices stacked vertically, the effective bitcell size projected on the substrate is only about 0.0081 squaremicrons. As a result, a 50 mm² chip with 50% array efficiency in a 0.18micron technology and with 8 layers of memory devices would haveapproximately 3.1 billion memory cells for a capacity of approximately386 megabytes with two bits stored per cell and 193 megabytes with onebit stored per cell. The three-dimensional versions of the memory use anextension to three dimensions of the “virtual ground array” commonlyused with single crystalline silicon memory devices. The preferredmemory process architecture uses N+ doped polysilicon railsperpendicular to rail stacks of P− doped polysilicon/charge trappinglayer/N+ polysilicon in a cross-point array forming NMOS transistormemory devices with a SONOS charge trapping layer which may beduplicated vertically. Of course a PMOS memory can also be made.

Adjacent pairs of N+ polysilicon rails and a rail stack of P− dopedpolysilicon/charge trapping layer/N+ doped polysilicon define thesource, drain and gate, respectively, of a unique NMOS memory device.Programming and erasing change the threshold voltage of this NMOS. Withhot electron injection programming, two bits per NMOS can be stored anderasing can be performed either with hot hole injection or withFowler-Nordheim tunneling.

Turning now to FIG. 80, a method of integrating memory devices inaccordance with a specific embodiment of the present invention into amulti-level array of storage cells will now be described. Thefabrication starts by providing a substrate 5180 on which the multilevelarray of storage devices is to be formed. Substrate 5180 will typicallyinclude a lightly doped monocrystalline silicon substrate 5182 in whichtransistors such as metal oxide semiconductor (MOS) transistors areformed. These transistors can be used as, for example, accesstransistors or they can be coupled together into circuits to form, forexample, charge pumps or sense amps for the fabricated memory devices.Substrate 5180 will typically also include multiple levels ofinterconnects and interlayer dielectrics 5184 used to couple transistorsin substrate 5182 together into functional circuits. The top surface5186 of substrate 5180 will typically include an insulating layer orpassivation layer to protect the underlying transistors andinterconnects from contamination. The top surface 5186 will typicallycontain electrical contact pads to which multilevel arrays of memorydevices of the present invention can be electrically coupled in order tomake electrical contact with the transistors in silicon substrate 5182.In an embodiment of the present invention, the memory devices arephysically isolated and separated from the single crystalline substrateby multiple levels of interconnects and dielectric 5184. The top surfaceof passivation or insulating layer 5186 will typically be planarized toenable uniform and reliable fabrication of multiple levels of the memorydevices of the present invention. According to the present invention,the memory devices are physically separated from monocrystalline siliconsubstrate 5182. In an alternative embodiment of the present invention,memory devices can be fabricated on a glass substrate 5180 such as usedin flat panel displays.

A process of forming a multilevel array of thin film transistor (TFT)memory devices above the substrate in accordance with an embodiment ofthe present invention begins by blanket depositing a first conductorlayer 5188 over surface 5186 of substrate 5180. Conductor 5188 can beany suitable conductor such as, but not limited to, titanium silicide,doped polysilicon, or a metal such as aluminum or tungsten and theiralloys formed by any suitable technique. Conductor layer 5188 is to beused as, for example, a bitline or a wordline to couple a row or columnof memory devices together. Next, a planarization is performed bydepositing or growing an insulating layer such as a silicon oxide overconductor layer 5188 to fill spaces between bit lines. A conventionalchemical mechanical polishing (CMP) step completes the planarization andexposes the bitlines.

Turning now to FIG. 66, a specific embodiment of the present inventionis illustrated in front perspective view. In this embodiment, a2-dimensional memory array 5040 includes a first plurality ofspaced-apart conductors such as N+ doped polysilicon bit lines 5042,5044, 5046, 5048 disposed in a first direction a first height over (notin contact with) the substrate (not shown). A second plurality ofspaced-apart “rail stacks” 5050, 5052 are disposed in a second directiondifferent from the first direction (and preferably orthogonally) at asecond height above the substrate so that they are above bit lines 5042,5044, 5046 and 5048 and in contact therewith at intersection points5054, 5056, 5058, 5060, 5062, 5064, 5066, 5068. Each rail stack 5050,5052 in this embodiment includes at least a layer of P− dopedpolysilicon 5070 which may be formed, for example, by depositing anamorphous silicon film by chemical vapor depositing (CVD) and which isin situ doped with P type impurities (e.g., Boron) to a dopant densityof about 1×10¹⁶ to about 1×10¹⁸ atoms/cm³. The amorphous silicon filmscan then be converted into polycrystalline silicon through a subsequentanneal step. Alternatively, instead of in situ doping, undoped siliconcan be grown or deposited and then implanted or diffused with dopants.Over layer 5070 is disposed a charge trapping layer 5072 comprising acharge trapping medium as discussed below, and a conductive wordline5074 which may comprise N+ doped (or P+ doped) polysilicon disposed overthe charge trapping layer 5072. A planarized oxide material (not shownin FIG. 66) may be deposited in the spaces between and above adjacentbit lines and rail stacks. A conventional chemical mechanical polishing(CMP) process may be used to accomplish the planarization.

The memory array structure of FIG. 66 can now be easily extrapolated tothree dimensions. To do this, the CMP planarized oxide layer overwordlines 5050, 5052 is used. The planarized isolation layer (orinterlayer insulating layer) prevents shorting one set of wordlines withthe next set of bit lines. Then another layer of bit lines 5042, 5044,5046, 5048 is constructed over the isolation layer followed by an oxidedeposition and a CMP step, followed by a deposition of another set ofwordlines. This process can be repeated a number of times, as desired.In accordance with a specific embodiment of the present invention, eightlayers of memory array (or more) are stacked one upon another to provide8 times the bit density of the non-three-dimensional version.

Turning now to FIG. 67, another specific embodiment of the presentinvention is illustrated. In this embodiment a 2-dimensional array 5076includes an isolation layer 5078 electrically separating it from thesubstrate (not shown). The isolation layer may be any conventionalisolation/insulation layer such as a silicon oxide. Over isolation layer5078 is disposed a plurality of spaced-apart bit lines 5080, 5082, 5084,5086. Bit lines 5080, 5082, 5084, 5086 are preferably formed of N+ dopedpolysilicon although P+ doped polysilicon could also be used as couldany suitable electrical conductor. A deposition step is used to fill theregions 5088, 5090, 5092 between adjacent bit lines 5080, 5082, 5084,5086 with a filler material. The filler material must be an electricalinsulator. Again, silicon oxide is convenient although other materialscould also be used. A CMP step is then used to planarize and expose thebit lines. A layer 5094 of a semiconductor material such as P− dopedpolysilicon is then disposed over and in contact with bit lines 5080,5082, 5084, 5086. An ONO layer 5096 is disposed over the semiconductorlayer 5094 and a conductive wordline 5098 is disposed over ONO layer5096. In accordance with a presently preferred embodiment, the bit lines5080, 5082, 5084, 5086 and the wordlines 5098 are formed of N+ dopedpolysilicon. When thermally processed, N+ out diffusion regions 5100,5102, 5104, 5106 are formed in P− doped semiconductor layer 5094. Thechannels 5108, 5110, 5112 between adjacent N+ out diffusion regionsbecome channels of NMOS transistors whose threshold voltages arecontrolled by the presence or absence of trapped charge in the nitridelayer of ONO dielectric stack 5096.

Those of ordinary skill in the art will realize that semiconductors ofthe opposite conductivity types may also be used. Where a conductorother than doped polysilicon is used for the wordlines and bit lines itwill be necessary to form a doped region in semiconductor layer 5094 insome way other than by out diffusion.

FIG. 68 is a top plan view of the memory array of FIG. 67. As shown inFIG. 68, the wordlines 5098 are arranged over the bit lines 5080 in across point array. While the wordlines and the bitlines are arrangedperpendicular (i.e., at a 90 degree angle) to each other in FIG. 68, anangle between the wordlines and bitlines may differ from 90 degrees.Furthermore, outside the boundaries of the memory array, the wordlinesand the bitlines may change directions and even be parallel to eachother. Furthermore, the term “rail stack” or “rail” preferably refers toconductors arranged in straight lines. However, if desired, the rails orrail stacks may have bends, twists or turns, if desired.

Turning now to FIG. 69 the memory array of FIG. 67 is extrapolated to amonolithic three-dimensional array. The term “monolithic” means thatlayers of each level of the array were directly deposited on the layersof each underlying level of the array. In contrast, two dimensionalarrays may be formed separately and then packaged together to form anon-monolithic memory device. Each device level 5076 is preferablyidentical to that shown in FIG. 67 and an isolation layer (i.e.,interlayer insulating layer) 5078 separates each level. A single cell(i.e., a TFT EEPROM) 5099 is delineated by the dashed line in FIG. 69.The cell 5099 is located in device level “j” at the intersection of wordline (n,j) and bit lines (m,j) and (m+1,j).

Turning now to FIG. 70, another specific embodiment of the presentinvention is illustrated. In this embodiment, an array of bottom gateTFTs is formed. A two-dimensional memory array 5114 is disposed above asubstrate. An isolation layer 5116 is disposed to separate memory array5114 from the substrate (not shown) or another level of memory array(not shown). A plurality of spaced-apart wordlines 5118 are disposedover isolation layer 5116. Over wordline 5118 are disposed a film of acharge trapping medium 5120, such as an ONO dielectric stack. Over thecharge trapping medium 5120 is disposed a plurality of spaced-apartbitlines 5122, 5124, 5126, 5128. In the space 5130, 5132, 5134 betweenbit lines 5122, 5124, 5126, 5128 is disposed a film of semiconductormaterial 5136. This may be deposited into spaces 5130, 5132, 5134 or itmay be deposited or grown over charge trapping medium 5120 and thenmasked and etched so that bitlines 5122, 5124, 5126, 5128 are formedafter it has been formed. This version of the memory array approximatesturning the design of FIG. 69 upside down. In this way, the bitlines aretrenches that would be filled by N+ doped polysilicon. Prior to filling,n-type implantation is carried out to form the MOS devices' sources anddrains. In addition, a refractory metal may be used at the bottom of thetrenches instead of dopant to form the sources and drains.

Turning now to FIG. 71 the memory array of FIG. 70 is extrapolated to amonolithic three-dimensional array. Each level 5114 is preferablyidentical to that shown in FIG. 70 and an isolation layer 5116 separateseach level.

Turning now to FIG. 72, another specific embodiment of the presentinvention is illustrated, where each bit line acts as a bit line forTFTs in two device levels. In this embodiment a memory array 5140includes a lower word line 5142 and an upper word line 5144. Bitlines5146, 5148, 5150, 5152 are disposed between upper wordline 5144 andlower wordline 5142. In a manner similar to that of FIG. 67 and FIG. 69,an upper semiconductor film 5154 is disposed between bitlines 5146,5148, 5150, 5152 and upper wordline 5144. Lower semiconductor film 5156is disposed between bitlines 5146, 5148, 5150, 5152 and lower wordline5142. Out diffusion regions are formed adjacent to bitlines 5146, 5148,5150, 5152 in upper semiconductor film 5154 and lower semiconductor film5156. A lower charge storage medium film 5158 is disposed between lowerwordline 5142 and lower semiconductor film 5156. An upper charge storagemedium film 5160 is disposed between upper wordline 5144 and uppersemiconductor film 5154. Notice that in this embodiment the layers arecopied in a mirror image fashion.

Turning now to FIG. 73, the memory array of FIG. 72 is extrapolated to amonolithic three dimensional array. Each device level 5140 may bethought of as containing two word lines and two TFT active regions and aplurality of bit lines disposed between the active regions.Alternatively, each device level may be thought of as a single wordline5142 being disposed between two TFT active regions. Thus, each devicelevel contains either one wordline level and two bitline levels or onebitline level and two wordline levels. Each TFT active region sharesboth a bitline and a wordline with another TFT active region disposed ina different horizontal plane.

An alternative bottom gate TFT embodiment is illustrated in FIGS. 81A-81 H. The approach of FIGS. 81A-81H is somewhat similar to that ofFIG. 70. Layer 5116 is an isolation layer such as an oxide separatingthe memory array structure 5114 from other memory array levels or fromthe substrate. Layer 5118 is a conductive wordline layer. Layer 5120 isan O—N—O dielectric stack. Layer 5136 is a film of semiconductormaterial (p-type when the wordlines and bitlines are N+ polysilicon).

In FIG. 81B an oxide layer 5190 is deposited or grown. In FIG. 81C theoxide layer 5190 is masked with a mask 5192 (i.e., a photoresist mask).In FIG. 81D the unmasked portions of the oxide layer 5190 are etched ina conventional manner.

In FIG. 81E the mask 5192 is removed and semiconductor layer 5136 isimplanted with n-type ions to form an N+ implantation region 5194 ateach opening in the oxide layer 5190 as illustrated in FIG. 81F. In FIG.81 G an N+ layer 5196 is deposited to fill gaps in the oxide and formbitline 5198 of N+ material in contact with N+ implantation regions 5194so as to provide a contact with the O—N—O layer 5120. In FIG. 81H the N+layer 5196 is CMP planarized as shown to form the bitlines 5198, tocomplete an NMOS TFT array. Of course a PMOS TFT array may beconstructed by reversing the conductivity types of the layers anddopants. A multilayer version of the memory array of FIGS. 81A-81H canbe constructed by forming additional device levels separated by anisolation layer.

Another alternative embodiment of a top gate TFT array is illustrated inFIGS. 82A-82I. In FIG. 82A an oxide or isolation layer 5200 is disposedabove a substrate (not shown). In FIG. 82B a layer of semiconductormaterial of a first conductivity type 5202 is disposed over oxide layer5200. The semiconductor material may be P− doped amorphous silicon. Overthis in FIG. 82C is deposited a hard nitride CMP-stop layer 5204 to stopthe CMP process from polishing into layer 5202.

In FIG. 82D the memory array under construction is masked with mask5206, as a photoresist mask. In FIG. 82E an etch is being carried out toform apertures or trenches 5208 as shown in FIG. 82F. In FIG. 82G aconductive layer 5210 is deposited, such as n+ doped polysilicon. InFIG. 82H this layer 5210 is CMP polished down leaving N+ bitlines 5212with P− doped regions 5214 between them. After thermal processing, outdiffusion regions 5216 are formed as shown in FIG. 821. Furthermore, theamorphous silicon layer 5202 is recrystallized into a polysilicon layer.

In FIG. 82I a local charge storage film 5218 is disposed over bitlines5212 and a conductive film 5220 is disposed over local charge storagefilm 5218. The conductive film 5220 is patterned to form a wordline. Thecharge storage film 5218 is also patterned to form rail stacks whichinclude the wordline and the charge storage film.

The charge storage medium film used herein (also referred to herein as a“local charge storage film”) needs to be able to retain a localizedcharge, i.e., it must not laterally conduct. In one embodiment, a chargetrapping layer may be formed in a dielectric stack 5160 as shown in FIG.77. For example, the charge storage medium can be a dielectric stack5160 comprising a first oxide layer 5162 adjacent to a polysilicon film5164, a nitride layer 5166 adjacent to the first oxide layer 5162 and asecond oxide layer 5168 adjacent to the nitride layer 5166 and adjacentto a polysilicon control gate 5170. Such a dielectric stack 5160 issometimes referred to as an ONO stack (i.e., oxide-nitride-oxide) stack.Other suitable charge trapping dielectric films such as siliconimplanted or silicon-rich oxides can be used if desired.

The charge storage medium film may alternatively be formed from aplurality of electrically isolated nanocrystals 5172 as shown in FIG.78. Nanocrystals are small clusters or crystals of a conductive materialwhich are electrically isolated from one another. An advantage of theuse of nanocrystals for the charge storage medium is that because theydo not form a continuous film, nanocrystals are self isolating.Nanocrystals 5172 enable multiple self-isolating charge storage areas tobe formed.

Nanocrystals 5172 can be formed from conductive material such assilicon, tungsten or aluminum. In order to be self isolating thenanocrystals must have a material cluster size less than one-half thepitch of the cell so that floating gates from vertically andhorizontally adjacent cells are isolated. That is, the nanocrystals ormaterial clusters 5172 must be small enough so that a single nanocrystal5172 cannot bridge vertically or horizontally adjacent cells. Siliconnanocrystals can be formed by depositing silicon in a manner wherebysilicon has a very high surface diffusivity relative to its stickingcoefficient. For example, silicon nanocrystals can be formed by chemicalvapor deposition (CVD), by decomposing silane (SiH₄) at a very lowpressure, in a range of about 1 millitorr to about 200 millitorr, at atemperature in a range of about 250° to about 650° C. In such a process,a very thin deposition, in a range of about 50 Å to about 250 Å, willform little islands of silicon. If H₂ is included with silane during thedeposition, higher pressures can be utilized and still obtainnanocrystals. In an alternative embodiment of the present invention,metal nanocrystals such as aluminum nanocrystals, can be formed bysputtering from a metal target at a temperature near the meltingtemperature of the metal, so that the metal agglomerates and formsnanocrystals. Tungsten nanocrystals can be formed by chemical vapordeposition at very low pressures by utilizing a reactant gas mixcomprising a tungsten source gas such as WF₆ and germane (GeH₄). Instill yet another embodiment of the present invention, a continuous filmof floating gate material can be deposited and then caused toprecipitate (by heating) to cause islands to form in the film.

It is to be appreciated, that although nanocrystals are preferred forthe floating gate, because of their self isolating quality, the floatinggate can be formed from a continuous film such as, but not limited to, ametal such as tungsten or a silicon film such as polycrystalline oramorphous silicon doped to the desired conductivity type (typically N+silicon). If a continuous film is used as a local charge storage film,the film would be anisotropically etched at this time to remove portionsof it in order to electrically isolate strips of the film.

Similarly, small pieces of floating gate material, such as heavily dopedpolysilicon, may form a local charge storage medium when embedded in aninsulator such as an oxide layer.

An issue with using N+ out diffusion in a multi-level device is that thevarious levels will be exposed to different thermal processing. That is,the bottom layer will be exposed to each thermal processing step whilethe top layer is only exposed to the last thermal processing steps.Since it is undesirable to have the MOS memory transistors exhibitingsubstantially different performance characteristics depending upon levelin the array and it is undesirable to allow lateral diffusion to swampthe MOS memory transistors, care needs to be given to the thermal budgetand mechanisms for forming source/drain regions. Where N+ doping is usedfor the bitline and P− doping for the semiconductor film, it is possibleto use antimony as the dopant instead of phosphorous as antimonyexhibits a smaller diffusivity than phosphorous. It is also possible toengineer the dopant profile in the bitline polysilicon to allowdifferent out diffusions. This is shown in FIG. 76 in schematicrepresentation. After polysilicon dopant difflusion is characterized forvarious thermal budgets for the polysilicon depositions, one can easilydetermine how far away the N+ in situ doped material should be from theP− doped body region as a function of memory level within the array.Antimony could also be used here and could be directly implanted, ifdesired. In FIG. 76, the bitlines denoted (a) are closer to the toplevel of the memory array than are the bitlines denoted (b). In otherwords, bitlines (a) are located above bitlines (b) in the array. Duringthe thermal treatment, the dopants in the bitlines will diffuse upwardsthroughout the entire bit lines and outdiffuse into the P− polysiliconlayer to form the source and drain regions. Thus, the source and drainregions in plural levels will be evenly doped.

Turning now to FIG. 69, to program the first bit in the selected cell inFIG. 69, WL(n,j) is pulsed high (9-13V, high impedance) while BL(m,j) isgrounded and BL(m+1,j) is pulsed high (3-8V, lower impedance). All BL'sto the left of BL(m,j) on the j^(th) level are held at ground while allBL's to the right of BL(m+1,j) on the j^(th) level are held at the samevoltage as BL(m+1,j). All other WL's on the j^(th) level are held atground to make sure that all other MOS devices between BL(m,j) andBL(m+1,j) are off. All other BL's and WL's on all other layers can beleft floating. This means that the selected cell MOS device is uniquelyon and powered to optimize hot carrier generation and programming intothe charge trapping dielectric close to the drain (defined byBL(m+1,j)).

To read the first bit, BL(m+1,j) is now the source and BL(m,j) is thedrain. The former is grounded and the latter is raised to a read voltage(˜50 mV to 3V, preferably 1-3V) while WL(m,j) is pulsed to a readvoltage (1-5V). Again, all BL's to the left of BL(m,j) are held at thesame potential as BL(m,j) and all BL's to the right of BL(m+1,j) aregrounded. All other WL's on the same level are grounded to shut off allother MOS devices between the same two BL's. All other BL's and WL's onall other levels can be left floating.

To program and read the second bit in the same cell, the voltages onBL(m,j) and BL(M+1,j) are reversed compared to the above.

Notice that the body region of the MOS memory transistor is floating andcan be made thin (defined by the deposition tool, e.g., preferablyseveral hundred Angstroms). By making this region thin, snapback of thedevice can be avoided and so rapid increase in programming currents canalso be avoided.

Erasing of the memory can take place in blocks and may employ acombination of slow Fowler-Nordheim tunneling and hot hole in,jection.The erase current will be small since the MOS body is floating resultingin very little band-to-band tunneling and avalanche breakdown. Erase cantake place with the wordlines either grounded or held negative (˜−5V)and all bitlines held at some positive voltage. The erase procedure willtake over 100 ms and can be done at each memory level up to the fullmemory at one time.

Non-selected bits with common wordline should be able to withstand theprogramming voltage on the wordline for a worst case period of time.FIG. 74 shows this in schematic detail in one level of the matrix.

If each bit (i.e. half cell) needs time t to program and there are Ncells on each WL then, in a worst case, a programmed bit wouldexperience (2N-1)t of time where the programming voltage would beapplied to the WL. The gate stress program disturb would be fine if anyprogrammed cell did not shift its Vt by a certain “minimal” amount.Since programming is achieved using hot electrons, the times andvoltages are short and small respectively compared to voltages and timesneeded to tunnel out of charge traps. In addition, the total stress onany one bit may be effectively reduced by floating unselected bitlinesduring the programming of the selected cell. In this way, only theselected bitline at ground will experience a true full programmingvoltage across the dielectric(s).

Non-selected bits with a bitline in common with the selected bit shouldbe able to withstand the programming voltage on the drain for a worstcase period of time. FIG. 75 shows this in schematic detail where across section along a bitline is shown.

Again, if there are M cells on any one bitline and it takes time t toprogram any one bit, then the worst case drain stress on a programmedbit will be (M-1)t in time. So the Vt shift in a programmed bit afterexperiencing such a stress should be minimal.

Read disturb or “soft write” occurs if the hot carriers generated duringa read of the cell are sufficient to eventually (over 10 years lifetime)program a previously erased (unwritten) bit. Accelerated testing isusually carried out here to make sure that the read voltages required donot shift the threshold voltage of a neutral cell by more than a minimalamount.

In the devices set forth above, N+ or P+ doped polysilicon should bedoped to a dopant density of about 1×10¹⁹ to 1×10²¹ atoms/cm³ and have athickness preferably in a range of about 500 Å to about 1000 Å. P− or N−doped semiconductor films should be doped to a dopant density of about1×10¹⁶ to about 1×10¹⁸ atoms/cm³.

It is to be appreciated that each of the memory devices shown can bemade of opposite polarity by simply reversing the conductivity type ofeach of the silicon regions and maintaining dopant concentration ranges.In this way, not only can NMOS devices be fabricated, but also PMOSdevices can be formed if desired. Additionally, the silicon films usedto form the device may be recrystallized single crystal silicon orpolycrystalline silicon. Additionally, the silicon film can be a siliconalloy film such as a silicon germanium film doped with n-type or p-typeconductivity ions to the desired concentration.

Where it is desired to increase the lateral conductivity of polysiliconwordlines and bitlines, a layer of a conductive metal may be depositedin the wordline or bitline as illustrated in FIG. 79. In FIG. 79 bitline5174 is formed of polysilicon 5176 which is heavily N+ doped. This makesit electrically conductive. To further reduce electrical resistance, alayer of a refractory electrically conductive metal such as titanium5178 may be disposed within the bitline 5174, or on one or more surfaceof the polysilicon 5176. When subjected to normal silicon processingtemperatures the titanium forms a silicide with the polysilicon that ishighly conductive in a lateral direction.

IV. Flash Memory Array in a Rail Stack Configuration

In the previous embodiments, the TFTs were arranged in a virtual groundarray (VGA). In a VGA illustrated in the previous embodiments, theprogramming of each EEPROM occurs by hot carrier in,jection. In hotcarrier in,jection, a voltage is placed across a diode (i.e., between asource and a drain of a TFT EEPROM). The hot carriers (i.e., hotelectrons and holes) that are travelling from source to drain throughthe channel of the TFT EEPROM are in,jected into the charge storageregion which is disposed adjacent to the channel. This procedure is arelatively high power event.

For low power portable applications where both program/erase and readpower are important, a flash nonvolatile memory using Fowler-Nordheimtunneling (“FN tunneling”) for both program and erase may be used. FNtunneling results from applying a voltage across a dielectric. Thus, ina TFT EEPROM, a voltage is applied between a control gate and a sourceand/or a drain) region of the TFT, for writing and erasing the TFTEEPROM. This is in contrast with hot carrier in,jection programming,where a voltage is applied between the source and the drain regions.

A flash memory array which uses FN tunneling for program and erase isadvantageous because thousands of bits in such a flash memory array maybe programmed at the same time.

Also, FN tunneling is a very efficient way of programming since most(close to 100%) of the current goes to program the device. This is incontrast with hot carrier injection where only about 1-2% of thesource-drain current goes to program the device.

Thus, in a preferred embodiment of the present invention, charge storagedevices, such as TFT EEPROMs, are arranged in a flash memory arrayconfiguration. The TFT EEPROMs may be arranged in the pillar,self-aligned TFT or rail stack configurations of the previousembodiments. Preferably, the TFT EEPROMs are arranged in the rail stackconfiguration.

The VGA is not compatible with FN tunneling since the whole channelpolysilicon inverts along the length of the pulsed-high word line andwill then program cells in addition to the one that needs programming.Therefore, the FN tunneling rail stack (crosspoint) flash array differsfrom the VGA in that in the FN tunneling array the active polysiliconlayer is patterned into polysilicon islands to allow FN tunnelingprogramming. Thus, an extra photolithographic masking step is added tothe process of making the rail stack array during which the polysiliconactive layer is etched into islands in each device cell. The samephotoresist mask can be used to define (i.e., etch) the charge storageregions in each cell.

FIG. 83A illustrates a flash memory array in a rail stack configurationaccording to a preferred embodiment of the present invention. FIG. 83Bshows a cross sectional view along line B-B in FIG. 83A.

In FIG. 83A, the flash memory array 5230 is preferably formed over aplanarized interlayer insulating layer 5231, such as a CMP planarizedsilicon oxide layer. Layer 5231 is formed over a substrate (not shown)as in the previous embodiments. Each device of the array (shown bydashed lines 5232 in FIG. 83A) is thus a TFT because it is formed overan insulating layer.

The array 5230 contains a first plurality of spaced-apart conductive bitlines 5233 disposed at a first height above the substrate in a firstdirection. The array also contains a second plurality of spaced-apartrail-stacks 5235. The rail stacks are disposed at a second height in asecond direction different from the first direction. Preferably, the bitlines 5233 and the rail stacks 5235 are arranged perpendicular to eachother. The TFT EEPROM 5232 is formed at the intersection of the railstacks 5235 and the bit lines 5233.

Each rail-stack 5235 includes a plurality of semiconductor islands 5237,which comprise the active regions of the TFT EEPROMs 5232. One surfaceof the islands 5237 is in contact with the bit lines 5233. Each railstack 5235 also includes a conductive word line 5239 and a chargestorage region 5241 disposed between a second surface of thesemiconductor islands 5237 and the word line 5239.

The semiconductor islands 5237 preferably comprise polysilicon of afirst conductivity type (i.e., P− or N−). However, the islands maycomprise amorphous silicon if desired. The polysilicon islands 5237include source and drain regions 5243 of a second conductivity type(i.e., N+ or P+). The source and drain regions 5243 are located atcontacting intersections between the bit line conductors 5233 and therail stacks 5235.

The bit lines 5233 preferably comprise polysilicon of the secondconductivity type (i.e., N+ or P+). The bit lines 5233 contact thesource and drain regions 5243. Preferably, the source and drain regionsare formed by outdiffiusion of dopants from the bit lines. Furthermore,an optional metal or a metal silicide layer (not shown in FIG. 83A) maybe disposed in contact with the bit lines 5233 to increase theconductivity of the bit lines. The space between said spaced-apart bitline conductors 5233 is filled with a planarized insulating fillermaterial 5245, such as silicon oxide.

The charge storage regions 5241 may comprise a dielectric isolatedfloating gate, electrically isolated nanocrystals or an O—N—O dielectricstack, as in the previous embodiments. An exemplary array having adielectric isolated floating gate is illustrated in FIGS. 83A and B.Thus, in the example of FIGS. 83A and B, the charge storage region 5241comprises a polysilicon floating gate 5247 between a tunnel dielectric5249, such as a silicon oxide layer, and a control gate dielectric 5251(also known as the intergate or interpoly dielectric) made of a materialsuch as silicon oxide or an ONO layer stack.

As shown in FIGS. 83A and B, the lateral sides 5253 of the tunneldielectric 5249 and the floating gate 5247 are aligned to the lateralsides 5255 of the semiconductor islands 5237. The control gatedielectric 5251 extends between the semiconductor islands 5237 andcontacts the planarized insulating material 5245 between thesemiconductor islands 5237. If desired, the floating gate 5247 may bemade from hemispherical grain polysilicon which has a textured surfaceto maximize the control gate to floating gate coupling. Alternatively,the coupling may be increased by increasing the floating gate height, byforming horns or protrusions in the floating gate, or by roughening thefloating gate surface.

The word line 5239 comprises a polysilicon layer of a secondconductivity type (i.e., N+ or P+) and a metal or a metal silicide layerin contact with the polysilicon layer. The word line 5239 acts as acontrol gate of the TFT EEPROM in locations where it overlies the chargestorage regions 5241. Thus, formation of a separate control gate foreach TFT is not required.

In one preferred aspect of this embodiment, the rail stacks 5235 aredisposed above the bit lines 5233, as shown in FIGS. 83A and B. However,if desired, the rail stacks 5235 may be disposed below the bit lines5233 in each device level, as described with respect to FIG. 70 in aprevious embodiment (i.e., bottom gate TFT EEPROMs are formed).

As shown in FIG. 83B, the word line 5239, the charge storage regions5241 and the semiconductor islands 5237 (i.e., the rail stacks 5235) arealigned in a plane 5256 perpendicular to the substrate and parallel to asource to drain direction. The rail stacks 5235 are separated by asecond planarized insulating layer 5257, such as silicon oxide.

While the flash memory array may comprise a two dimensional array,preferably, the flash memory array comprises a monolithic threedimensional array comprising a plurality of device levels. For example,three device levels are shown in FIG. 83A. The device levels areseparated by an interlayer insulating layer 5259, such as a siliconoxide layer. If desired, layers 5257 and 5259 may comprise the samesilicon oxide layer which is deposited above and between the rail stacks5259, and then planarized by CMP.

To program the selected TFT EEPROM 5232, either its drain bit line orits source bit line 5233 (or both) are grounded while the positiveprogramming voltage is applied to the selected word line 5239 adjacentto the device 5232 (which is a high impedance node). All other wordlines on the same device level are grounded while all other bit lines onthe same level device can float or are placed at a slight positivevoltage. This means that only the selected cell 5232 experiences theprogramming voltage across it. Through capacitive coupling, the floatinggate 5247 is pulled high while the source and/or drain 5243 aregrounded. Electrons tunnel to the floating gate 5247 from the sourceand/or drain 5243 and an inversion channel is formed in the siliconchannel 5237. The current to program such a cell to get a thresholdvoltage shift of about 5V in approximately one millisecond is severalpicoamps.

To erase the cell, the same bit lines 5233 can be grounded and anegative voltage pulse is applied to the selected word line 5239. Allother word lines can either be grounded or can float. All other bitlines float or are placed at a slight negative voltage. A plurality (orall) of EEPROM cells in the array can be erased at the same time bypulsing a plurality of word lines to a high negative value while all bitlines are grounded. Alternatively, the selected wordline is groundedwhile the selected cell's bit lines are pulsed positive. All other wordlines float or are pulsed slightly positive while all the other bitlinesare grounded.

Programming and erasing using FN tunneling alone allows use of lowcurrent programming and erasing, which lends itself to “massiveparallelism” in programming and erasing. Therefore, many cells 5232 canbe programmed in parallel. For example, to get 5V shift, one thousandcells would need about 2 nA in total current and would program in about1 microsecond per cell, average. During programming and erasing, theparasitic leakage currents are small because no large voltages areplaced across polysilicon diodes (i.e., source/channel/drain junctions).During reading, the parasitic leakage currents are also small becausesource to drain voltages are also small. A programming voltage of 10-20Vmay be used to program the cells. In the above approach of FIGS. 83A andB, a small cell size is achieved. However, only positive thresholdvoltages (for NMOS TFT EEPROMs shown in FIGS. 83A and B) are attainable,since otherwise large amounts of parasitic bit line to bit line leakageresults. In order to allow both positive and negative threshold voltagesin each cell, an access transistor (i.e., a TFT MOSFET) is added to eachcell in a second preferred aspect of the flash memory array, as shown inFIG. 84.

FIG. 84 illustrates a built-in access transistor 5261 in each cell whosethreshold voltage can be set to a slight positive value. By using theaccess transistor 5261, the actual cell transistor (i.e., the TFT EEPROM5232) can have a negative threshold voltage without introducing bit lineleakage and avoiding special erase-and-check algorithms that preventover-erase. Furthermore, the access transistor can also reduce thedefect-based TFT band-to-band tunneling leakage that may occur atnegative gate voltages and could be problematic in programmed cells(i.e., floating gate full of electrons), (see S—H Hur et al., “A Poly-SiThin-Film Transistor EEPROM Cell with Folded Floating Gate”, IEEE Trans.Elect. Dev., vol. 46, pp. 436-438, February 1999, incorporated herein byreference).

As shown in FIG. 84, the semiconductor islands 5237 contain adjacentchannel regions 5263, 5265 of the access transistor 5261 and the EEPROM5232, respectively, between the common source 5243A and drain regions5243B. The word lines 5239 form control gates of the EEPROMs and gateelectrodes of the access transistors. An insulating layer 5251 forms acommon control gate dielectric of the EEPROM and a gate insulating layerof the access transistor. The floating gate 5247 and a tunnel dielectric5249 are located between the word line 5239 and the channel region 5265of the EEPROM 5232.

To program the floating gate 5247 of a cell 5232/5261, its source bitline 5233A is grounded, its drain bit line 5233B floats, and a highpositive voltage pulse is applied to the selected cell's word line. Thistunnels electrons to the floating gate. All other bit lines on the samedevice level are left floating or are placed at a slight positivevoltage while all other word lines on the same level are grounded. Toread, the selected cell's word line is pulsed to a read voltage of abovethe access transistor's threshold voltage while the cell's source bitline is grounded and drain bit line is set at a low positive voltage,such as 1 to 3 V. All other bit lines at the same level are leftfloating or grounded while all word lines at the same level aregrounded. To erase the cell, its word line is pulsed to a high negativevalue while its source bit line is grounded. To erase the whole array,all word lines can be pulsed to a high negative value while all sourcebit lines are grounded.

In another preferred aspect of the flash memory array, a gate to drainoffset region 5267 is provided to reduce TFT band-to-band defect relateddrain leakage, as shown in FIG. 85. Thus, in the example of FIG. 85, theword line 5239 and the charge storage region 5241 are offset apart fromthe drain region 5243B. A thick insulating layer 5269 is located betweenthe semiconductor islands 5237 and the word lines 5239 in the offsetregion 5267. The floating gates 5247, the tunnel dielectric 5249 and thecontrol gate dielectric 5251 have aligned lateral sides 5253A and B.Only one of the lateral sides 5253A is aligned to the lateral side 5255Aof the semiconductor islands 5237. The islands 5237 have a greater widththan the floating gates 5247, the tunnel dielectric 5249 and the controlgate dielectric 5251.

If desired, ONO or isolated nanocrystal charge storage regions may beused instead of the floating gate charge storage regions in theembodiments of FIGS. 84 and 85. Furthermore, the devices of FIGS. 84 and85 may be formed in a bottom gate configuration (i.e., with the bitlines above the word lines) if desired.

In the flash memory array of FIGS. 83A and B, each cell size per bit isabout 8 F²/N to about 10 F²/N, where F is a minimum feature size and Nis a number of device levels in the array. In the flash memory array ofFIGS. 84 and 85, each cell size per bit is about 9 F²/N to about 11F²/N. Thus, a cell size per bit of about 8 F²/N to about 11F²/N, may beachieved. This cell size compares favorably with cell sizes ofcommercially available flash memory arrays, which range from 7.7 F² to13.9 F². If the access transistors and contacts are factored in theeffective cell size of the commercially available devices, then due toredundancy, their cell size ranges from 9.8 F² to 19.2 F². However, whenthe flash memory array of the present embodiment is formed as a threedimensional array (i.e., N>1), then the cell size per bit of the flashmemory array of the present embodiment is significantly smaller thanthat of the prior art. For example, for N=2, the cell size is about 4 F²to about 5.5 F². For N>2, the cell size is even smaller.

The method of making the flash memory array of FIGS. 83-85 isillustrated in FIG. 86. FIGS. 86A-D illustrate a method of making theflash memory array where the word lines are disposed above the bit linesin each device level. A plurality of spaced-apart bit line conductors5233 are formed at a first height above the substrate (not shown) byetching a first conductive layer using a first photoresist mask. The bitline conductors 5233A and B extend in a first direction, as shown inFIG. 86A. Preferably, the bit lines comprise polysilicon and metal ormetal silicide layers. A first insulating layer 5245 is deposited aboveand between the bit line conductors 5233A, B. The insulating layer 5245is planarized by CMP until the top surface of the bit line conductors5233A, B is exposed.

A stack of layers including a first semiconductor layer 5237 and acharge storage film are deposited on the exposed bit line conductors5233A, B and the planarized insulating layer 5245, as shown in FIG. 86B.Layer 5237 may be an amorphous silicon or a polysilicon layer. In FIG.86B, the charge storage film comprises a tunnel dielectric layer 5249and a floating gate polysilicon layer 5247. Alternatively, the chargestorage film may be an ONO stack or dielectrically isolatednanocrystals.

A second photoresist layer (not shown) is formed on the stack andphotolithographically patterned into a mask. Using this photoresistlayer as a mask, the stack of layers 5237, 5249 and 5247 is etched toform a plurality of first rail stacks 5271 (only one such rail stack isshown in FIG. 86C for clarity). The first rail stack 5271 extends in thesame or substantially the same direction as the bit line conductors 5233in a plane parallel to the substrate. Each of the first rail stacks 5271contains a semiconductor rail 5237 and a charge storage region rail5247/5249. The first rail stacks 5271 have at least one aligned lateraledge 5253/5255. In FIG. 86C, the first rail stacks 5271 have two suchaligned lateral edges since each first rail stack is patterned using thesame photoresist mask, which is removed after the etching step.

If floating gate type EEPROMs are to be formed, then the control gateinsulating layer 5251 is deposited over the first rail stacks 5271 andin the spaces 5273 between the first rail stacks, as shown in FIG. 86D.Thus, layer 5251 extends beyond the lateral edges of the first railstacks 5271. If an ONO or isolated nanocrystal type EEPROMs are to beformed, then the semiconductor layer 5237 would be deposited andpatterned into first rail stacks 5271 after deposition. Then the ONO orthe nanocrystal containing layer would be deposited over the patternedfirst rail stacks 5271, followed by the deposition of a conductive layer5239 for the wordline.

A second conductive layer 5239 is deposited over the control gateinsulating layer 5251. Preferably, layer 5239 comprises polysilicon andmetal silicide sublayers. A third photoresist mask (not shown) is formedover the second conductive layer 5239. The second conductive layer 5239,the control gate dielectric 5251 and the first rail stacks 5271 are thenetched to form a plurality of second rail stacks 5235, as shown in FIG.86D. The second rail stacks comprise the patterned second conductivelayer which forms the word line 5239, charge storage region islands5247/5249/5251 and the semiconductor islands 5237.

The source 5243A and drain 5243B regions are formed by outdiffusingdopants of a second conductivity type (i.e., N+ or P+) into thesemiconductor islands 5237 of a first conductivity type (i.e., P− or N−)from the first plurality of spaced-apart conductors. The source anddrain regions may be formed at any time during the fabrication sequenceafter the semiconductor layer 5237 is deposited on the bit lineconductors 5233A, 5233B. For example, the device may be annealed afterthe formation of the second rail stacks 5235 to outdiffuse the dopantsinto the source and drain regions and to recrystallize the amorphoussilicon layer 5237 into a polysilicon layer (or to increase the layer5237 grain size). The outdiffusion anneal and the crystallization annealmay occur during the same or during separate heating steps. For example,the recrystallization anneal may take place right after layer 5237 isdeposited.

The side surfaces of the second rail stacks 5235 are aligned in a planeperpendicular to the substrate and parallel to a direction which extendsfrom the source 5243A to the drain 5243B of the TFT EEPROM 5232, asshown in FIG. 83B. The control gate dielectric 5251 is disposed betweenthe word line 5239 and the first insulating layer 5245. Since thecontrol gate dielectric is part of the first rail stacks 5235, thecontrol gate dielectric 5251 is aligned in a plane perpendicular to thesubstrate and parallel to a source to drain direction to thesemiconductor islands 5237, the tunnel dielectric 5249, the floatinggates 5247 and the control gates 5239, as shown in FIG. 83B. The firstrail stacks 5271 are converted into islands during the etching of thesecond rail stacks 5235.

A second insulating layer 5257 is then deposited over the second railstacks 5235 and planarized by CMP to be level with the second railstacks, as shown in FIG. 83B. An interlayer insulating layer 5259 isthen deposited over the second insulating layer 5257 and the second railstacks 5235. If desired, a single insulating layer may be depositedabove and between the second rail stacks 5235 to form the secondinsulating layer 5257 and the interlayer insulating layer 5259. Thesingle layer is then planarized by CMP. If desired, a plurality ofadditional device levels of the array may be monolithically formed abovelayer 5259 to form a three dimensional monolithic array having at leastthree device levels, as shown in FIG. 83A. Each device level ispreferably separated by an interlayer insulating layer.

In an alternative method of making the flash memory array, the word linein each device level may be formed below the bit line conductors (i.e.,bottom gate TFT EEPROMs rather than top gate TFT EEPROMs are formed). Inthe alternative method, the second rail stacks 5235 comprising the gatelines 5239, the charge storage regions 5251/5247/5249 and thesemiconductor islands 5237 are formed first, as shown in FIG. 86E. Then,the first insulating layer 5245 is formed on the semiconductor islandsof the second rail stacks 5235. The first insulating layer 5245 may alsobe formed between the second rail stacks if desired. Alternatively,another insulating layer is formed between the second rail stacks andplanarized by CMP prior to the formation of the first insulating layer5245.

Trenches are then formed in the first insulating layer 5245. Source anddrain regions 5243 are formed in the semiconductor islands 5237 by ionimplanting (or diffusing) dopant ions through the trenches. Thephotoresist layer (not shown) used during the etching of the trenchesmay be removed before or after the ion implantation. A second conductivelayer (such as a layer comprising polysilicon and silicide sublayers) isformed in the trenches and over the first insulating layer, as shown inFIG. 86F. The second conductive layer is then planarized by CMP to formthe bit line conductors 5233 overlying the semiconductor islands 5237.Alternatively, the source and drain regions 5243 may be formed byoutdiffusion from the bit line conductors 5233 rather than by ionimplantation.

Similar methods may be used to form the flash memory array having TFTEEPROMs with an access transistor, as shown in FIG. 84 or having TFTEEPROMs with a drain offset region, as shown in FIG. 85. In thesemethods, the stack of layers which includes a tunnel dielectric layer5249 and a floating gate layer 5247 are deposited over the firstsemiconductor layer 5237, as shown in FIG. 86C. The stack of layers isthen patterned to form first rail stacks 5271 which includesemiconductor rails 5237 having a first width and charge storage regionrails 5247/5249 having a second width smaller than the first width, suchthat the first rail stacks have one aligned lateral edge and drainportions of the semiconductor rails 5237 are exposed.

Such a structure may be achieved by two different etching methods. Thefirst etching method includes forming a first photoresist mask 5275having a first width over the stack, as shown in FIG. 86G. The firstsemiconductor layer 5237, the tunnel dielectric layer 5249 and thefloating gate layer 5247 are then etched using the first photoresistmask 5275, as shown in FIG. 86G. A second photoresist mask 5277, havinga second width smaller than the first width, is then formed over thefloating gate layer 5247. The tunnel dielectric layer 5249 and thefloating gate layer 5247 but not the first semiconductor layer 5237 arethen etched using the second photoresist mask as shown in FIG. 86H.

The second etching method includes forming a first photoresist mask 5279having a first width over the stack and etching the tunnel dielectriclayer 5249 and the floating gate layer 5247 using the first photoresistmask 5279 to expose a portion of the first semiconductor layer 5237, asshown in FIG. 861. Then a second photoresist mask 5281, having a secondwidth larger than the first width, is formed over the floating gatelayer 5247 and over an exposed portion of the first semiconductor layer5237 (it is possible that there may be some misalignment between layer5281 and layers 5249/5249). The first semiconductor layer 5237 is thenetched using the second photoresist mask 5281, as shown in FIG. 86J.

To form the TFT EEPROMs with an access transistor 5261 of FIG. 84, acontrol gate dielectric layer 5251 is formed over the patterned floatinggates 5247 and over the exposed portions of the semiconductor rails 5237of the first rail stacks 5271. The control gate dielectric layer 5251functions as a gate dielectric of the access transistor 5261 over theexposed portions of the semiconductor rails 5237.

To form the TFT EEPROMs with a drain offset region 5267 of FIG. 85, thecontrol gate dielectric layer 5251 is patterned at the same time as thefloating gate layer 5247 and the tunnel dielectric layer 5249, to exposethe drain portion and part of the channel silicon of the semiconductorrails 5237. A second insulating layer 5269 is then formed over thecontrol gate dielectric 5251 and the exposed portion of thesemiconductor rails 5237, as well as between the semiconductor rails5237 to isolate the semiconductor rails from each other. Layer 5269 isrelatively thick, having a thickness that is the same as or greater thanthe thickness of the charge storage regions 5241. Layer 5269 is thenplanarized by CMP to expose the top portion of the charge storageregions. The word line 5239 is then formed over the second insulatinglayer 5269 to form the offset regions 5267.

The nonvolatile, multiprogrammable flash memory array of the preferredembodiment provides many-times -programmable cells in a crosspoint(i.e., rail stack) array. FN tunneling is used for program and erase.This allows many cells to be written in parallel and provides highdensity, low power file storage. In addition, the cell sizes per layercompare very favorably with cell sizes of commercially available flashmemories.

V. CMOS Array for Logic and Memory Circuits

In the previous embodiments, arrays of NMOS or PMOS devices weredescribed. However, in another preferred embodiment of the presentinvention, an array of CMOS (complementary metal oxide semiconductor)transistors is provided. Preferably, adjacent NMOS and PMOS transistorshave a common gate. However, the adjacent NMOS and PMOS transistors mayhave separate gates if desired. The array of CMOS devices may comprisean array of vertical pillar CMOS devices, an array of self aligned CMOSTFTs or an array of rail stack TFTs, as described in any previousembodiment. The CMOS devices are preferably formed as a threedimensional monolithic array above the substrate. However, the CMOSdevices may also be formed in a two dimensional array in or above asemiconductor substrate, if desired.

The NMOS and PMOS transistors of the CMOS array may be formed adjacentto each other in the same device level in an alternating fashion (i.e.,as alternating NMOS and PMOS transistors). However, in a preferredembodiment of the present invention, the one charge carrier typetransistors (i.e., NMOS or PMOS) are formed above the other chargecarrier type transistors (i.e., PMOS or NMOS) with a common gate line(also known as a word line in memory devices) between them. Thus, thearray preferably comprises a plurality of vertically stacked, commongate CMOS transistors.

FIG. 87 illustrates one device level of a vertically stacked, commongate CMOS array in a rail stack configuration according to a preferredembodiment of the present invention. It should be noted that the arraymay also be arranged in a self aligned TFT or pillar configurationsdescribed previously. The CMOS array in FIG. 87 is similar to the arrayillustrated in FIG. 73, except that transistors of different chargecarrier type are formed on either side of the gate line. In FIG. 87, theNMOS transistors are arranged below the PMOS transistors. However, itshould be understood that the PMOS transistors may be arranged below theNMOS transistors if desired.

In FIG. 87, the array of CMOS devices 5300 is preferably formed over aplanarized interlayer insulating layer 5301, such as a CMP planarizedsilicon oxide layer. Layer 5301 is formed over a substrate (not shown)as in the previous embodiments. Each CMOS device is thus a CMOS TFTbecause it is formed over an insulating layer. However, the CMOS devicesmay be formed in a monocrystalline silicon substrate, if desired.

The array includes a plurality of gate lines (i.e., word lines) 5303(only one gate line is shown in the cross sectional view of FIG. 87).Preferably the gate line comprises a first N+ polysilicon layer 5305, asilicide layer 5307, such as a TiSi_(x) or WSi_(x) layer, over the firstpolysilicon layer and a second P+ polysilicon layer 5309 above thesilicide layer. The gate line 5303 acts as a gate electrode in each TFT.Thus, no separate gate electrodes connected to the gate lines arerequired.

A first insulating layer 5311 is disposed adjacent to a first side ofthe gate electrode 5303. This insulating layer 5311 may be aconventional gate dielectric. Preferably, the insulating layer 5311 is acharge storage layer (i.e., charge trapping media), such as an ONO stackor isolated nanocrystals, to form charge storage CMOS TFTS, such asEEPROM CMOS TFTs. If floating gate type EEPROM CMOS TFTs are desired,then a floating gate and a control gate dielectric may be added betweenthe insulating layer 5311 and the gate line 5303.

A p-type semiconductor layer 5313, such as a P− polysilicon layer, isdisposed on a side of the first insulating layer opposite to the gate5303. This layer contains the NMOS TFT bodies. N+ source and drainregions 5315 are disposed in layer 5313. The portions of layer 5313between regions 5315 comprise NMOS TFT channel regions.

Preferably, the source and drain regions 5315 are formed byoutdiffiusion of n-type dopants from the source and drain electrodes(i.e., bit lines) 5317. However, regions 5315 may be formed by any othermethod, such as by masking and ion implantation. The electrodes 5317contact the source and drain regions 5315 and are disposed on the bottomof the p-type semiconductor layer 5313 (i.e., on the side of layer 5313opposite to the first insulating layer 5311). Preferably, the electrodes5317 comprise N+ polysilicon rails which extend in a directionperpendicular to the gate line 5303. If desired, an optional metal ormetal silicide layer is formed in contact with electrodes 5317 toincrease their conductivity. However, the electrodes 5317 may comprisemetal or metal silicide instead of the heavily doped polysilicon, ifdesired. A planar insulating filler layer 5318, such as silicon oxide,is disposed between the source and drain electrodes 5317.

Thus, each NMOS TFT 5319 is located between adjacent source and drainregions 5315 and comprises a portion of layers 5305, 5311, 5313 and5317, as illustrated in FIG. 87. The PMOS TFTS 5321 are located abovethe NMOS TFTs 5319.

The PMOS TFTs 5321 include a second insulating layer 5323 adjacent to asecond side of the gate electrode 5303. In FIG. 87, layer 5323 islocated on the P+ polysilicon layer 5309 of the gate line 5303. Theinsulating layer 5323 may be a conventional gate dielectric. Preferably,the insulating layer 5323 is a charge storage layer (i.e., chargetrapping media), such as an ONO stack or isolated nanocrystals, to formcharge storage CMOS TFTS, such as EEPROM CMOS TFTs. If floating gatetype EEPROM CMOS TFTs are desired, then a floating gate and a controlgate dielectric may be added between the insulating layer 5323 and thegate line 5303.

An n-type semiconductor layer 5325, such as an N− polysilicon layer, isdisposed above the second insulating layer 5323. Layer 5325 is disposedon the opposite side of layer 5323 from the gate electrode 5303. P+source and drain regions 5327 are disposed in layer 5325, such thatregions of layer 5325 between the source and drain regions 5327 comprisechannel regions of PMOS TFTs. Source and drain electrodes 5329 aredisposed over the N− polysilicon layer 5325 and in contact with thesource and drain regions 5329. Thus, the electrodes 5329 are disposed ontop side of the N− polysilicon layer 5325 opposite to the secondinsulating layer 5323. A planar insulating filler layer 5331, such assilicon oxide, is disposed between the source and drain electrodes 5329.If desired, an optional metal or metal silicide layer is formed incontact with electrodes 5329 to increase their conductivity.

Thus, each PMOS TFT 5321 is located between adjacent source and drainregions 5327 and comprises a portion of layers 5309, 5323, 5325 and5329, as illustrated in FIG. 87. A TFT EEPROM CMOS device (5319 and5321) is formed at each intersection of the first and the thirdspaced-apart electrodes or conductors 5317, 5329 and the common gateline 5303. If desired, the CMOS structure may be inverted and the PMOSTFTs formed below NMOS TFTs. It should be noted that NMOS and PMOSelectrodes (i.e., bit lines) do not have to fall directly on top of eachother, although they preferably should have the same pitch. NMOS andPMOS transistors thus can have different channel lengths, but the pitch(and thus array size) will be limited by the longer of the two channellengths. In one preferred aspect, TFTs of one conductivity type (i.e.,NMOS or PMOS TFTs) contain a charge storage layer or region, while TFTsof the other conductivity type (i.e., PMOS or NMOS) do not have a chargestorage region or layer. Thus, the CMOS of this aspect comprises oneEEPROM TFT and one non-EEPROM TFT.

The TFT CMOS device array 5300 illustrated in FIG. 87 is highly planarand compact. The NMOS source and drain electrodes 5317 comprisepolysilicon rails which extend above the interlayer insulating layer5301 in a first plane parallel to the substrate surface. The p-typepolysilicon layer 5313 extends above the source and drain electrodes5317 in a second plane. The gate line 5303 extends above layers 5317,5313 and 5311 in a third plane. The n-type polysilicon layer 5325extends above the gate line 5303 in a fourth plane. The PMOS source anddrain electrodes 5329 comprise polysilicon rails which extend above then-type semiconductor layer 5325 in a fifth plane. Each of the fiveplanes does not intersect any of the other planes.

The TFT CMOS array 5300 is also self aligned. The gate electrode 5303,the first insulating layer 5311, the p-type semiconductor layer 5313,the second insulating layer 5323 and the n-type semiconductor layer 5325comprise a rail stack which is located in a plane parallel to thesubstrate. The rail stack extends perpendicular to the source and drainelectrodes 5317, 5329. Thus, the gate electrode 5303, the firstinsulating layer 5311, the p-type semiconductor layer 5313, the secondinsulating layer 5323 and the n-type semiconductor layer 5325 are selfaligned in a plane perpendicular to the substrate and parallel to thesource to drain direction, as will be described in more detail below.

The TFT CMOS array 5300 is preferably arranged in a monolithic threedimensional array comprising a plurality of device levels verticallyseparated by one or more interlayer insulating layers. Each device levelthe array contains TFT CMOS devices 5300, as in the previousembodiments. A peripheral or driver circuit (not shown) is arranged inthe substrate, preferably below the array and at least in partialvertical alignment with the array, or alternatively, within or above thearray and at least in partial vertical alignment with the array.

FIGS. 88A-D illustrate a method of making the rail stack TFT CMOS array5300 according to a preferred embodiment of the present invention.First, an N+ polysilicon layer is deposited and patterned to form thesource and drain electrodes or conductors 5317. An insulating layer5318, such as a silicon dioxide layer, is then deposited over andbetween the conductors 5317. Layer 5318 is then planarized by CMP toform a planarized block 5331, as shown in FIG. 88A. The top surfaces ofthe conductors 5317 are exposed in the top surface of the block.

A stack of layers is then deposited on the block 5332. These layersinclude the p-type polysilicon (or amorphous silicon) layer 5313, thefirst insulating or local charge storage film 5311, the gate layer 5303,the second insulating or charge storage film 5323 and the n-typepolysilicon (or amorphous silicon) layer 5325. A photoresist mask (notshown) is then formed over this stack, and the stack of layers ispatterned to form a plurality of rail stacks 5333 (only one rail stack5333 is shown in FIG. 88B for clarity). The mask may be removed afterall the layers have been patterned. Since all of the layers in railstack 5333 are patterned during the same step, the layers in the railstack 5333 are self aligned in a plane perpendicular to the substrate(i.e., the sides of the rail stack 5333 are planar). The rail stacks5333 are disposed above the block 5332. The rail stacks extend in adifferent direction from the direction of the electrodes 5317.Preferably, the rail stack 5333 and the electrodes 5317 extend inperpendicular directions within the array, as shown in FIG. 88B.

An insulating layer 5331, such as a silicon oxide layer, is thendeposited over the rail stack 5333, such that it fills in the spaces5335 between the rail stacks 5333, as shown in FIG. 88C. Layer 5331 isthen planarized by CMP. A photoresist mask (not shown) is formed onlayer 5331, and parallel trenches 5339 are etched in layer 5331 usingthe mask. The trenches extend parallel to the electrodes 5317 andperpendicular to the rail stacks 5333, as shown in FIG. 88C.

If desired, optional sidewall spacers (not shown) are formed on thesidewalls of the rail stack 5333 before the deposition of layer 5331.Preferably, the spacers are made from an insulating material that isdifferent from the material of layer 5331. The spacers are preferablymade of silicon nitride. The spacers protect the sidewalls of the stack5333 during the etching of the trenches. The spacers keep the trenchetch from extending too far past the top of the gate lines in the areabetween gate lines, to protect against gate to source/drain shorts.

Using layer 5331 and/or the photoresist as a mask, p-type ions (i.e.,boron or BF₂) are implanted into the exposed n-type semiconductor layer5325 through the trenches 5339. The ions form P+ source and drainregions 5327 in layer 5325, as shown in FIG. 88D.

A p-type polysilicon layer is then deposited over layer 5331 and in thetrenches 5339. The polysilicon layer is planarized by CMP or etched backto form a plurality of spaced apart P+ electrodes 5329 embedded in theplanarized insulating layer 5331. The electrodes 5329 are located abovethe rail stacks 5333 and contact the P+ source and drain regions 5327.Since the electrodes 5329 and source and drain regions 5327 are formedduring the same lithography step, there is no misalignment between theelectrodes 5329 and source and drain regions 5327. Alternatively, thesource and drain regions 5327 may be formed by outdiffusion from theelectrodes 5329 rather than by ion implantation into the trenches 5339.

The array is annealed to form N+ source and drain regions 5315 byoutdiffusion from N+ electrodes 5317 and to recrystallize the amorphousor polysilicon semiconductor layers 5313 and 5325. The outdiffusion andrecrystallization may be carried out during the same or differentannealing steps at any desired point in the fabrication process.

If desired, an interlayer insulating layer is formed over the arrayshown in FIGS. 87 and 88D, and another device level containing anotherarray of TFT CMOS EEPROM devices 5300 is monolithically formed thereon.Routing metallization layers (preferably a metal layer other thanaluminum) may be formed in the interlayer insulating layer. Additionalinterlayer insulating layers and device levels may be formed over thesecond level of the array if desired, to form at least three devicelayers. In another alternative aspect of this embodiment, a second railstack containing a gate line is formed directly on top of the PMOSelectrodes 5329 without an intervening interlayer insulating layer.Thus, the PMOS electrodes 5329 would contain source and drain regions intwo rail stacks. In other words, plural device levels may be formedwithout intervening interlayer insulating layers to form a threedimensional monolithic array. This arrangement offers more transistorswith fewer processing steps, but with less programming flexibility.

As shown in FIG. 89, the resulting TFT CMOS array is a matrix of NMOS5319 and PMOS 5321 devices with common gates 5303. The array shown inFIG. 89 is an unprogrammed or unconfigured array. The array can then beconfigured into logic elements or memory devices by rupturing the gatedielectric (i.e., the charge storage film or region) to form aconductive link which connects the gate lines (i.e., word line rows)5303 and source and drain electrodes 5317, 5329 (i.e., bit lines), or bystoring charge in the charge storage regions of either NMOS or PMOStransistors to raise their threshold voltages and keep them permanentlyoff. The array of TFT CMOS EEPROM devices 5300 may be used to formeither logic elements or a memory array. Furthermore, the samesemiconductor device in the unconfigured array may be used either as anantifuse or as an EPROM or an EEPROM.

According to a preferred embodiment of the present invention, a circuitcomprising a plurality of charge storage devices and a plurality ofantifuse devices is provided. The circuit may comprise a fieldprogrammable gate array or a programmable logic device. Preferably, theplurality of charge storage devices and the plurality of antifusedevices comprise a same set of devices. This greatly simplifies thefabrication of the circuit. These devices function as charge storagedevices when a first programming voltage is applied to the devices toturn these devices off by increasing their threshold voltage. Thesedevices also function as antifuses when a second programming voltagehigher than a first voltage is applied to the devices. The secondvoltage may be any voltage which is sufficient to form a conductive linkthrough the charge storage region. For example, the first (i.e., chargestorage voltage) may be less than 5 volts, while the second voltagesufficient to form the conductive link may be 5-50 volts, depending onthe device characteristics. The voltages are provided to the devices bythe driver or peripheral circuit. However, if desired, charge storageand antifuse semiconductor devices having a different structure may beprovided.

It should be noted that any charge storage devices which function as anantifuse when a conductive link has been formed through its chargestorage region are within the scope of the present invention. Thus, anydevice is within the scope of the present invention if the devicecontains a semiconductor active region, a charge storage region adjacentto the semiconductor active region, a first electrode and secondelectrodes, and where charge is stored in the charge storage region whena first programming voltage is applied between the first and the secondelectrodes, and a conductive link is formed through the charge storageregion to form a conductive path between the first and the secondelectrodes. Therefore, a charge storage device which is capable of beingused as an antifuse is not limited to rail stack TFT EEPROMs. Suchcharge storage devices may include the pillar or self aligned TFTEEPROMs and diodes with charge storage regions of the previousembodiments, as well as EPROMs and EEPROMs formed in a single crystalsemiconductor substrates. FIG. 90 illustrates how a 4×4 cell array ofthe circuit of FIG. 89 can be programmed into an inverter 5343. First, ahigh voltage is applied between gate (i.e., word) line 5345 and bitlines 5347, which will be used to carry the output voltage, V_(out).This causes conductive antifuse links 5348 to form to electricallyconnect lines 5345 and 5347. Then, the driver circuit provides aprogramming voltage to all other transistors 5350 to increase theirthreshold voltage to turn them off, except to NMOS transistors 5355 andPMOS transistors 5357. The NMOS 5355 and PMOS 5357 transistors form theinverter. When a high voltage, V_(in), is provided into gate line 5349,then a low voltage, V_(out), is read out, and vice-versa. VoltagesV_(SS) (i.e., ground) and V_(DD) (i.e., power supply voltage) areprovided into bit lines 5351 and 5353 which are connected to transistors5355 and 5357.

FIG. 91 illustrates how a 4×4 cell array of the circuit of FIG. 89 canbe programmed into a two input NAND gate 5360. First, a high voltage isapplied between gate (i.e., word) line 5345 and bit lines 5347, whichwill be used to carry the output voltage, V_(out). This causesconductive antifuse links 5348 to form to electrically connect lines5345 and 5347. Then, the driver circuit provides a programming voltageto all other transistors 5350 to increase their threshold voltage toturn them off, except for PMOS transistors 5361 and 5365 and NMOStransistors 5363 and 5365. The transistors 5361, 5363, 5365 and 5367form the NAND gate. Input voltages V_(in1) and V_(in2) are provided intogate lines 5369 and 5371. CMOS 5361/5363 is connected to gate line 5369,while transistors 5365 and 5367 are connected to gate line 5371.Voltages V_(SS) and V_(DD) are provided into bit lines 5373 and 5375.NMOS 5367 is connected to bit line 5375, while PMOS 5361 and 5365 areconnected to bit line 5373. Output voltages can be read out from lines5345 or 5347, which are connected by a blown antifuse 5348.

FIG. 92 illustrates how a 5x6 cell array of the circuit of FIG. 89 canbe programmed into a static random access memory (SRAM) 5380. First, ahigh voltage is applied between gate (i.e., word) lines 5381 and 5383and bit lines 5385, 5386, 5387 and 5388. This causes conductive antifuselinks 5348 to form to electrically connect lines 5381 with lines 5385and 5386, and to electrically connect lines 5383 with lines 5387 and5388. Then, the driver circuit provides a programming voltage to allother transistors 5350 to increase their threshold voltage to turn themoff, except for transistors 5389, 5390, 5391, 5392, 5393 and 5394. Thetransistors 5389 and 5390 are the SRAM access transistors, whiletransistors 5391, 5392, 5393 and 5394 are the cross coupled inverters.The cell is accessed by placing a positive voltage on the word line5395. Data is input onto and read out of BL and BL-bar, which areprovided into bit lines 5396 and 5397, respectively. Voltages V_(SS) andV_(DD) are provided into bit lines 5398 and 5399, respectively.

FIGS. 89-91 show various exemplary configurations that can beprogrammed. It should be noted that any other desired logic or memorydevice, such as a NOR gate, etc., may be programmed using the methodsdescribed above. Since all logic fumctions can be performed by basicelements, such as NAND gates, any logic circuit can be programmed intothis type of an array. Furthermore, logic and memory devices may beprogrammed into the same circuit if desired. For logic devices, ingeneral, the size of the logic block is (x+1)² times the cell area,where (x) is the number of inputs on the logic gate. Since the cell areahere can be as small as 4 F², where F is the minimum feature size(half-pitch), then for F=0.25 microns, the minimum area per logic gateis 4(F(x+1))², or 2.25 microns squared for a 2-input NAND or NOR gate.Preferably, the area per logic gate is 4(F(x+1))² to 5(F(x+1))². Thissize includes an “isolation” row and column on each edge of the block,that is shared with the next block.

VI. Metal Induced Crystallization

A preferred embodiment of the present invention is directed to anon-volatile thin film transistor (TFT) memory or logic deviceconstructed above a substrate and including a source, drain and channelregion made of deposited or grown amorphous silicon or polysilicon thathas been crystallized by means of a transition metal-induced lateralcrystallization (MILC) process. A two- or, more preferably, athree-dimensional many-times programmable (MTP) non-volatile memory orlogic is constructed of such thin film transistor memory devices.

In accordance with the first aspect of the present embodiment, it isdesirable to improve the performance characteristics of TFT-basednon-volatile memory or logic cells having a channel formed in adeposited thin layer of silicon, such as amorphous silicon (a-Si) orpolysilicon. This can be accomplished if the grain size of the a-Si orpolysilicon can be increased to resemble monocrystalline silicon.

In the past, crystallization of a-Si has been accomplished in a numberof ways. In accordance with a first approach, a-Si may be partiallycrystallized to form polycrystalline silicon with an anneal step takingtens of hours at about 600° C. This approach is not advantageous becausethe devices formed in that material have lower-performancecharacteristics and they take a relatively long amount of time tofabricate. Thus, crystallization can be enhanced by the use oftransition metal or germanium catalysts to induce lateralcrystallization at seeding sites.

Unfortunately, most transistor-based devices fabricated in this mannersuffer from relatively poor performance characteristics (relative tomonocrystalline silicon) and exhibit subthreshold slope values on theorder of 100's of mV/dec and an Idsat of 10's of μA/μm. Themetal-induced lateral crystallization (MILC) is carried out at atemperature of about 400° C. to about 700° C. to achieve lateralcrystallization growth rates of several or more μm/hr. To furtherenlarge the silicon crystal sites to hundreds of microns, a relativelyshort duration high temperature anneal step, e.g., 900° C. for 30minutes, is added to simultaneously crystallize multiple layers of a-Si(or another semiconductor material). Note that a crystallizationtemperature range of about 750° C. to about 975° C. will also providesatisfactory results if the time of the anneal is adjusted accordingly.This short duration high temperature anneal will not saturate thediffusion regions of the devices contemplated herein and can be appliedonce to a multi-level device, as can the low temperature anneal step.

An example of a process for recrystallizing a deposited a-Si layer inaccordance with a specific embodiment of the present invention is nowdescribed and illustrated in FIGS. 93-95. Those of ordinary skill in theart will now realize that many routine modifications to the processillustrated here are possible and do not affect the inventive conceptsset forth herein.

Turning now to FIGS. 93-95, a process flow diagram of a fabricationprocess for a crystallized deposited (or grown) a-Si layer isillustrated in FIG. 93. FIGS. 94A-94H illustrate vertical cross sectionsof a silicon wafer prepared in accordance with the process of FIG. 93.FIG. 95 illustrates the effect of metal-induced lateral crystallization(MILC) through seeding windows 5424 in a-Si deposited over buried oxideover a standard silicon wafer.

The first step 5406 of the process 5408 is to grow (or deposit) a thickoxide layer 5410 (FIG. 94A) (e.g., 3000 Å) on a standard silicon wafersubstrate 5412 to provide a buried oxide layer. The next step 5414 is todeposit a thin amorphous silicon (a-Si) layer 5416 (e.g., 1000 Å) overburied oxide layer 5410. This can be accomplished, for example, with lowpressure chemical vapor deposition (LPCVD) at 550° C. using SiH₄ as thesilicon source at a flow rate of 70 SCCM and a pressure of 300 mtorr.Alternatively, layer 5416 may comprise a polysilicon layer. The nextstep 5418 is to deposit a sacrificial low temperature oxide (LTO) layer5420 (e.g., 3000 Å) and then in step 5419 to pattern it with mask 5422and etch to expose transition metal seeding widows 5424. These seedingwindows can be slots approximately 2 μm in width as shown in FIG. 95.Mask 5422 can now be removed.

The next step 5426 is to deposit a transition metal layer 5428 (e.g.,100 Å Ni (nickel)) over LTO layer 5420. Other transition metals may beused although Ni is presently preferred. Other transition metals whichmay also be used, but which are less desirable than Ni are: Fe (iron),Co (cobalt), Ru (ruthenium), Rh (rhodium), Pd (palladium), Os (osmium),Ir (iridium), Pt (platinum), Cu (copper) and Au (gold). Germanium mayalso be used if desired. The transition metal may also be introducedinto the seeding window by implantation and other mechanisms well knownto those of ordinary skill in the art.

The next step 5430 is to anneal for initial lateral crystallization.This step, illustrated in FIG. 94 F, may be carried out in a range oftemperature and times. For example, a 20 hour anneal at 560° C. in N₂ambient will work. Lower temperatures require longer anneal times,higher temperatures require shorter anneal times. Those of ordinaryskill in the art will now recognize that this can be optimized forthroughput considerations. This step performs a crystallization whichmay be adequate for certain devices and provide silicon grain sizes ofseveral to tens of μm. Other devices requiring even more performance andsilicon grain sizes in the hundreds of μm may require the hightemperature anneal step discussed below.

The next step 5432 is to strip the remaining transition metal layer5428. This may be performed with H₂SO₄:H₂O₂ (4:1) at 70° C. Then step5434 is the LTO layer 5420 is stripped with HF.

Finally, a high temperature anneal step 5436 (e.g., 900° C., 30 minutes,N₂ ambient) is conducted (if desired) to further crystallize thepartially crystallized a-Si to form even larger grain silicon crystals,(>100 μm in size). This step gives the crystallized a-Si layer (i.e., alarge grain polysilicon layer) performance characteristics similar toconventional SOI (silicon on insulator) CMOS technology. Note thattransition metal-crystallized semiconductor material as used herein willcontain trace detectable amounts of the transition metal(s) used forfacilitating the crystallization. In normal semiconductor processing,trace amounts of transition metals (typically Fe, Ni) will escape thestructure of the semiconductor fabrication equipment (usually containingstainless steel) and embed themselves into the semiconductor film wherethe TFT channel would be formed. Normally these transition metals arepresent at a level of less than about 10¹⁴ atoms/cc. In transition metalcrystallization, however additional trace amounts of transition metalsin excess of about 10¹⁴ atoms/cc and up to about 10¹⁸ atoms/cc willremain in the crystallized semiconductor material after processing. Thisis generally not a contamination problem, however, where it is desiredto create a gradient of such contaminants, a gettering material, e.g., P(phosphorous), may be placed in the source and/or drain regions of theTFT to reduce the concentration of such contaminants in the channelregion by increasing the concentration of such contaminants in therespective source and/or drain regions. Formation of devices in theregion of the seeding windows 5424 should be avoided due to excessivetransition metal contamination.

The above described metal induced crystallization method may be used torecrystallize the active semiconductor layer of any of the abovedescribed devices. Thus, pillar TFTs, self-aligned TFTs, rail stack TFTsand diodes (i.e., an active semiconductor layer which contains one ormore p-n junctions) of various configurations may be formed in therecrystallized a-Si or polysilicon.

VII. Metallization

In the various embodiments described above, a metal silicide layer wasformed in contact with a silicon layer, such as a polysilicon word lineor bit line. One preferred method of forming a titanium silicide layerin contact with a silicon layer is by using a silicon cap and a TiNlayer. The titanium silicide layer is formed on an undoped amorphoussilicon cap layer. The cap layer is formed on a heavily doped siliconlayer, such as a polysilicon or amorphous silicon layer doped to aconcentration in excess of 10¹⁹ cm⁻³, such as 10¹⁹ cm⁻³ to 10²¹ cm⁻³.The cap layer is preferably deposited on P+ polysilicon or N+ amorphoussilicon layers. The N+ amorphous silicon may then be recrystallized intoN+ polysilicon during subsequent annealing steps.

A method of forming a titanium silicide (TiSi₂) layer comprises thefollowing steps. A heavily doped polysilicon layer is deposited. Forexample, a P+ polysilicon layer is boron doped to a concentration of5×10²⁰ cm⁻³, and has a thickness of about 1400 Angstroms. A cap layer ofundoped amorphous silicon is deposited on the P+ polysilicon layer. Thecap may be 600 Angstroms thick, for example. A titanium layer isdeposited on the cap. The titanium layer may be 250 Angstroms thick, forexample. A titanium nitride layer is deposited on the titanium layer.The titanium nitride layer may be 100 Angstroms thick, for example.Other layer thicknesses may be used, as required.

The layers are annealed at a temperature below 650° C. for less thanfive minutes to react the titanium and the silicon in the cap to form aC49 phase TiSi₂ layer. The anneal may be carried out at 600° C. for 1minute, for example. If desired, another P+ polysilicon layer isdeposited over the stack and the stack is etched into a thin “wire” or“rail”, such as a word line or bit line. The wire or rail may be 0.25 mmwide or less. The titanium silicide is then transformed from the C49 tothe C54 phase by a high temperature (i.e., above 650° C.) anneal. Theanneal can take place before or after the wires or rails are patterned,at 800° C. for one minute, for example. By annealing each Si/Ti/TiN filmstack below 650° C., dopant diffusion and thermal grooving of the TiSi₂is minimized. Multiple film stacks can be deposited and etchedsequentially.

The foregoing description of the invention has been presented forpurposes of illustration and description. It is not intended to beexhaustive or to limit the invention to the precise form disclosed, andmodifications and variations are possible in light of the aboveteachings or may be acquired from practice of the invention. Thedrawings and description were chosen in order to explain the principlesof the invention and its practical application. The drawings are notnecessarily to scale and illustrate the arrays in schematic blockformat. It is intended that the scope of the invention be defined by theclaims appended hereto, and their equivalents.

1. An array of nonvolatile memory cells, wherein each memory cellcomprises a semiconductor device and each memory cell size per bit isabout (2 f²)/N, where f is a minimum feature size and N is a number ofdevice layers in a third dimension, and where N≧1.
 2. The array of claim1, wherein: the array comprises a monolithic three dimensional memoryarray, comprising a plurality of vertically separated device levels,where N>1; and the semiconductor device comprises a TFT EEPROMcomprising a channel, source and drain regions, and a charge storageregion.
 3. The array of claim 2, further comprising: a plurality of bitline columns in each device level, each bit line contacting the sourceor the drain regions of the TFT EEPROMs, and the columns of the bitlines extending substantially perpendicular to a source-channel-draindirection of the TFT EEPROMs; a plurality of word line rows in eachdevice level, and the rows of the words lines extending substantiallyparallel to the source-channel-drain direction of the TFT EEPROMs; andat least one interlayer insulating layer located between the devicelevels.
 4. The array of claim 3, wherein: the TFT EEPROMs furthercomprise control gates; and the plurality of word lines are self alignedto the control gates of the respective TFT EEPROMs, to the channelregions of the respective TFT EEPROMs, and to the charge storage regionsof the respective TFT EEPROMs located below the respective word lines.5. The array of claim 4, wherein the TFT EEPROMs further comprise:sidewall spacers located adjacent to sidewalls of the gates of the TFTEEPROMs, wherein the sidewall spacers have approximately the same heightas the gates; and an intergate insulating layer which is located betweenthe sidewall spacers, and above the source and the drain regions of theTFT EEPROMs in each device layer, and wherein the intergate insulatinglayer has approximately the same height as the sidewall spacers.
 6. Thearray of claim 5, wherein: the word lines are located on the sidewallspacers and on the intergate insulating layer in each device level; andthe word lines contact the respective TFT EEPROM control gates throughan opening between the sidewall spacers.
 7. The array of claim 3,wherein the TFT EEPROMs further comprise: floating gates located in thecharge storage regions; sidewall spacers located adjacent to sidewallsof the floating gates of the TFT EEPROMs; and an intergate insulatinglayer which is located between the sidewall spacers, and above thesource and the drain regions of the TFT EEPROMs in each device layer,and wherein the intergate insulating layer has approximately the sameheight as the sidewall spacers; and a control gate dielectric locatedabove the sidewall spacers and the intergate insulating layer and belowthe word lines.
 8. The array of claim 7, wherein the floating gatesextend vertically and laterally above the sidewall spacers, such thatthe floating gates have a “T” shape.
 9. The array of claim 3, furthercomprising word line contacts and bit line contacts which connect theword lines and the bit lines with peripheral circuits located in asemiconductor substrate below the first device level of the array; andwherein the bit line contacts extend between plural device layers.